Power.org introduces Power ISA Version 2.06

Power.org, an organisation that promotes and develops standards for Power Architecture technology, has released Power Instruction Set Architecture (ISA) Version 2.06.

Power ISA Version 2.06 is claimed to incorporate significant advances for server and embedded applications that improve performance and efficiency and speed design cycles.

Fawzi Behmann, marketing committee chair at Power.org, said: 'Power ISA Version 2.06 enhances Power Architecture capabilities for the server market and considerably extends Power Architecture technology's performance and design benefits for the embedded market.

'The Power.org ecosystem continues driving technology advances to align with the ever-evolving demands of the Power Architecture development community and applications, all driven by a need for high-performance and efficient operation.' Power ISA Version 2.06 defines significant extensions for the embedded environment, including an enhanced memory management architecture, logical partitioning and hypervisor support, embedded page table support and multi-threading.

It features: a vector-scalar floating-point facility that merges and extends existing vector and scalar floating-point operations; numerous fixed-point, floating-point and memory-management instructions; a storage attribute in support of strong storage access ordering; and storage control features.

For server applications, Power ISA Version 2.06 includes major extensions to the scalar and single-instruction multiple data (SIMD) floating-point architecture.

The Vector-Scalar Extension (VSX) unifies and extends the existing scalar floating-point and vector facilities to improve floating-point performance for compute-intensive tasks.

VSX introduces support for double-precision floating-point vector operations and consolidates the existing vector and floating-point scalar registers into a unified 64-entry register file.

These enhancements enable increased parallelism in double-precision floating-point processing with better execution pipeline utilisation, which is intended to lead to increased application performance.

For embedded designers, Power ISA Version 2.06 offers support for virtualisation and hypervisors, including a guest mode and memory management unit (MMU) extensions that are intended to enable the efficient implementation of hypervisors on the embedded Power Architecture platform.

It allows a more efficient implementation of virtualisation overall, partitioning of embedded systems, the isolation of applications and resource sharing and techniques that were previously only available for the server market.

The high-level memory management framework of previous architecture versions has been replaced by a detailed architecture based on the Freescale MMU model and has been extended to support virtualisation and enhanced performance.

This provides a single programming model to streamline future software development that formerly needed to cope with a variety of MMUs from multiple companies.

Page table support has been added to the embedded architecture specifically to enhance the performance of the Linux operating system running on embedded Power Architecture platforms.

This provides a more natural way to perform address translation and can significantly speed up applications where translation is a bottleneck.

Power ISA Version 2.06 includes explicit support for the execution of multiple threads on an embedded core.

Multi-threading is said to enable significant improvements in application throughput on the embedded platform.

Back to top