Product category:
Design and Development Software
News Release from: ProDesign | Subject: Chipit Platinum V4
Edited by the Electronicstalk Editorial
Team on 07 March 2006
Tool expands design debugging
functionality
ProDesign is integrating its newest Chipit Platinum V4 ASIC verification system with the Siloti Visibility Enhancement product introduced separately today by Novas Software.
ProDesign is integrating its newest Chipit Platinum V4 ASIC verification system with the Siloti Visibility Enhancement product introduced separately today by Novas Software The integration leverages ProDesign's new HCD Tool which expands the design debugging functionality of prototyping systems
This article was originally published on Electronicstalk on 24 Jan 2006 at 8.00am (UK)
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SoC verification platform turns to system design
The new member of the Chipit Platinum series features an enhanced system architecture based on Xilinx Virtex-4 FPGA technology, new debugging features and new software for system design.
Prototyping platform speeds ASIC verification
Chipit Gold Edition Pro is a cost effective, flexible and innovative high-speed prototyping platform that is applicable wherever functional ASIC design verification is required.
The integrated solution will provide users with very fast prototyping while enabling full internal design visibility for efficient debug.
The new Chipit Platinum V4 is based on the latest Xilinx Virtex-4 FPGA technology and equipped with the new HCD (host controlled debugging) mechanism.
The HCD tool allows users to have full access to the internal signal data from the FPGAs used in the scaleable Chipit Platinum System.
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ProDesign has released a PCI Express kit for its ASIC prototyping system Chipit Platinum Edition.
Interface aids transaction based verification
ProDesign has developed an SCE-MI based interface for transaction based verification for its successful Chipit ASIC prototyping product line.
Together, the Novas Siloti SilVE product and the HCD tool analyse and configure the system so that only the essential register values that need to be observed are extracted during operation.
That data is then expanded within the Siloti SilVE environment enabling full signal value visibility and correlated back to the original register transfer level (RTL) design description for debug with the Novas Verdi automated debug system.
The resulting methodology provides developers of multi-million-gate designs portioned over multiple FPGAs with greater observability of internal signal activity for faster verification and debug.
"We're delighted to collaborate with ProDesign to make it easier for engineers to observe and comprehend design behaviour during prototype verification and validation", said Scott Sandler, President and Chief Executive Officer of Novas.
"ProDesign's Chipit high speed verification systems and our Siloti and Verdi products help achieve this goal with new innovative technologies that provide full design visibility with minimal overhead for debugging complex problems".
"Today's generation of ASIC/SoC devices, and particularly large prototype designs containing multiple FPGAs on a single board, are becoming increasingly difficult to debug", said Gerhard Scherer, President of ProDesign Electronics Corporation.
"We are excited to take our collaboration with Novas to the next level, bringing together the benefits of high speed prototyping with enhanced verification and debug".
"Our new HCD tool, in combination with visibility enhancement capabilities from Novas, provides a mechanism for gaining valuable insight into the operation of multi-million-gate designs in the shortest possible time".
The HCD tool will be released in mid March, 2006.
It will be available for Chipit Master licences and supports up to 21 FPGAs in a system.
Like all Chipit software, the HCD tool will run on Linux, Solaris and Windows operating systems.
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