Auto router optimises yield

NexusRoute has been used by integrated circuit (IC) engineers to reduce design closure and manufacturing cycle time and increase chip yield by as much as 10%.

Pyxis Technology has released NexusRoute DFM-aware, yield-driven auto router that comprehends and optimises manufacturability and yield concurrently with the actual routing and timing closure process.

Designed for process technologies of 65nm and below, NexusRoute has been used by integrated circuit (IC) engineers to reduce design closure and manufacturing cycle time and increase chip yield by as much as 10%.

As silicon process technologies progress from 90 to 65nm and below, design engineers are faced with longer runtimes, more timing closure issues, and more iterations, both pre and post-tape-out, to handle the increasing effects of design-based yield limiters.

Design-based yield limiters result in lower chip performance, higher manufacturing costs and lower overall chip yield.

Because these limiters are chip layout-specific, they cannot simply be removed by product engineers working in a fab, but must be "designed out" from the very beginning of the design process.

At 45nm, existing routing architectures can no longer handle the complex interactions between design and process.

NexusRoute can be easily integrated into existing design flows using open industry standard interfaces.

It allows designers to scale with the newer technologies handle the complex design rules of nanometre technologies and simultaneously optimise designs for timing, manufacturability and yield.

The company has also released Pyxis Professional Services, a set of consulting and methodology services to help customers improve the yield on design blocks while assessing the impact of DFM design practices within their design environments.

Pyxis Technology has a team of design, manufacturing and EDA veterans with hundreds of man-years of experience in the design and manufacture of microprocessor and ASIC designs.

Pyxis Professional Services uses this knowledge to help customers maximise IC yield and manufacturability by leveraging DFM in their design environments.

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