Product category:
Programmable Logic Devices
News Release from: QuickLogic | Subject: QuickMIPS
Edited by the Electronicstalk Editorial
Team on 25 June 2001
Programmable and hard-wired logic embed
together
QuickLogic has revealed its upcoming QuickMIPS ESP family with a fully characterised processor system, market-specific hard-wired functions and the industry's fastest programmable logic.
QuickLogic has announced an architecture for the upcoming QuickMIPS ESP family with a fully characterised processor system, market-specific hard-wired functions and the industry's fastest programmable logic The complete development platform includes a QuickMIPS device, and a board support package with a real-time operating systems, as well as a timing model and reference design kit with emulation capability and drivers
This article was originally published on Electronicstalk on 14 Feb 2005 at 8.00am (UK)
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Based on the MIPS Technologies MIPS32 4Kc microprocessor core, the QuickMIPS solution delivers the guaranteed performance of ASSPs, an ASIC design flow and FPGA flexibility in a single system.
This platform will dramatically reduce full system design times in such advanced applications as Internet routers, VOIP, fibre-optic telecommunications switches and industrial control applications.
"By creating a platform using a programmable ASSP approach, we have dramatically reduced the complexity, performance and extended design and verification cycle challenges engineers face using soft IP and traditional blank-slate programmable logic", said Peter Feist, worldwide vice president of marketing for QuickLogic.
Further reading
Support for latest configurable logic devices
The ISA-QMIPS system analyser and FS2 Navigator logic analyser from First Silicon Solutions are optimised to support the recently announced QL902M, QL903M and QL904M QuickMIPS devices.
Linux tools are optimised for QuickMIPS
QuickLogic has optimised its suite of Linux tools for the QuickMIPS product family, including the recently announced QL902M, QL903M and QL904M devices.
Expansion for configurable MIPS processor lineup
Three new additions to the QuickMIPS product family target applications in communications, storage area networks and industrial control.
"Partnering with MIPS gives us the opportunity to offer the industry a high-performance processor ideal for today's embedded communications designs".
The foundation of the QuickMIPS system architecture is the completely verified and characterised functionality.
A 32bit advanced high-performance bus (AHB) allows quick access from both the processor and programmable logic to such high performance functions as Ethernet MAC, PCI, MMC (multifunction memory controller), Firewire (IEEE 1394) and USB 2.0.
A 32bit advanced peripheral bus (APB) enables access to lower-performance functions, such as timers, UARTs, and USB1.1.
Unlike traditional programmable logic attempts at system solutions, the QuickMIPS approach also includes hardwired master and slave bus interconnects to the programmable logic fabric to allow for easy instantiation of AMBA Bus compliant soft IP in the programmable fabric.
This concept saves system designers even more time and enables them to focus on adding value and differentiation.
The MIPS32 4Kc processor is optimised for the broadest range of system-on-chip applications and is hardwired as well as fully characterised and verified.
Key embedded functions, such as multiply-accumulate, are directly supported by MIPS MADD and MSUB instructions.
The QuickMIPS subsystem fully supports all MIPS-compatible instructions and design tools.
The QuickLogic programmable logic that enables customisation is the industry's fastest.
It includes high-speed logic cells, dual port RAM blocks and embedded computation units for math-intensive functions designed by customers.
The QuickMIPS design environment developed by First Silicon Solutions (FS2) offers the first on-chip instrumentation (OCI) solution that enables integrated debug of the programmable logic fabric and the CPU.
To accomplish this, FS2 enhanced the MIPS EJTAG (extended JTAG) with a configurable logic analyser (CLAM) that provides access to as many as 128 internal nodes (32 at a time).
Crosstriggering between the CLAM and the MIPS CPU enables instructions to be stopped and traced back to the fabric, thereby speeding software-hardware codesign and cosimulation.
The QuickMIPS devices and the system design package are expected to be available in 3Q 2001.
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