Product category:
Design and Development Software
News Release from: QuickLogic | Subject: QuickWorks version 9.1
Edited by the Electronicstalk Editorial
Team on 23 November 2001
Algorithms cut FPGA place and route in
half
QuickLogic has released version 9.1 of its QuickWorks development software.
QuickLogic has released version 9.1 of its QuickWorks development software Through a series of architecture-specific algorithm additions and improvements, the new tool increases ESP and FPGA programmable logic performance by an average of 40% while simultaneously reducing place and route times an average of 50%
This article was originally published on Electronicstalk on 8 Jul 2008 at 8.00am (UK)
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Specific performance-related enhancements to the QuickWorks software include a partition-based timing-driven placer, automatic clock buffer insertion, and various fan-out reduction techniques.
Together these improvements result in an average 40% device performance improvement over a series of benchmark designs.
The new placer also reduces place and route times by an average of 50% for the same benchmarks - resulting in dramatic overall design compilation time reductions for users.
A new GUI feature also enables users to prioritise device performance or compilation times.
In addition, QuickWorks v.
9.1 includes new DSP and SERDES configuration wizards, allowing users to quickly and easily create sophisticated, high-performance DSP and serial interface designs for QuickDSP and QuickSD ESP devices, respectively.
QuickWorks includes schematic entry and design compilation support.
Optional VHDL and Verilog synthesis support from Synplicity, and VHDL or Verilog functional and timing simulation support is available as well.
QuickWorks also supports a wide range of industry standard synthesis tools and simulators to ensure compatibility with existing design environments.
QuickWorks is available now for the Windows platform at $495.
A Unix version is also available now.
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