Product category:
Design and Development Software
News Release from: QuickLogic | Subject: Palace
Edited by the Electronicstalk Editorial
Team on 17 January 2002
Physical synthesis speeds ESP
development
QuickLogic and Aplus Design Technologies (ADT) have signed a multiyear agreement for QuickLogic to license ADT's Palace physical synthesis tool.
QuickLogic and Aplus Design Technologies (ADT) have signed a multiyear agreement for QuickLogic to license ADT's Palace physical synthesis tool Optimised for QuickLogic's ViaLink architecture, Palace is expected to offer speed grade improvements for ESPs (embedded standard products) through tightly coupled physical and logical cosynthesis
This article was originally published on Electronicstalk on 27 Mar 2001 at 8.00am (UK)
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Terms of the agreement were not disclosed.
"The integration of ADT's physical synthesis capabilities into QuickLogic's EDA toolchain will provide a fully automated, layout-driven synthesis to efficiently address timing closure and circuit performance challenges in submicron ESPs", said Peter Feist, QuickLogic's vice president of worldwide marketing.
"In addition, ADT's architecture-specific modelling and optimisation methodology, coupled with its IP modelling capabilities, will give us a state-of-art synthesis and compilation solutions for our growing range of highly integrated ESP families".
"We are pleased to work with QuickLogic to extend our physical synthesis technologies to QuickLogic's ViaLink architecture and embedded standard products", said Jason Cong, founder and president of ADT.
"QuickLogic's programmable technology and the range of ASSP content in its ESP families reduce interconnect delays and deliver a higher degree of system integration - a combination of attributes that are well aligned with our focus and core competency.
We see QuickLogic's choice of the Palace tool as another validation of ADT's physical synthesis capabilities".
Palace is expected to be available to engineers working with QuickLogic ESPs in Q3 2002.
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