Real-time analyser speeds QuickMIPS system designs

QuickLogic has released a real-time trace system analyser for its QuickMIPS development platform.

QuickLogic has released a real-time trace system analyser for its QuickMIPS development platform.

By delivering concurrent hardware and software debug, the FS2 system analyser for QuickMIPS speeds overall system designs and gives engineers added flexibility.

The FS2 system analyser is a key part of QuickLogic's complete system development kit (SDK) for the QuickMIPS platform, which includes a QuickMIPS device, and a board support package with a real-time operating system (RTOS), timing model and drivers.

Source level debugging is supported by Green Hills Software's Multi 2000 and Accelerated Technology's Codelab embedded developer suite.

"The complexity of system-chip designs increases dramatically when high performance processors are included", said Rick Leatherman, president and CEO of First Silicon Solutions.

"The FS2 system analyser is the first tool that allows an engineer to seamlessly debug the interdependencies between the programmable fabric and an embedded core".

"The QuickMIPS SDK with its expansion connector can be used as the prototyping board, which can save months of development time", said Lit Lam, senior director and general manager of QuickLogic's ESP product line.

"The new analyser extends those benefits to our integrated design environment by addressing the need for faster debugging".

The FS2 system analyser combines an enhanced MIPS EJTAG (extended JTAG) FS2 BlackBox debug probe with configurable logic analysis monitor (CLAM) on-chip logic in the QuickMIPS ESP to access as many as 128 internal nodes (32 of which can be traced simultaneously) in the QuickMIPS programmable fabric.

Trace information can be captured on-chip (standard) with up to 4K frames of trace depth.

An available option provides for high speed streaming of the trace off-chip with trace depth up to 128K, which saves on-chip resources for user logic.

Cross triggering between the CLAM and the MIPS32 4Kc microprocessor core enables instructions to be stopped and traced back to the state of various signals in the fabric, or triggers on specified conditions in the programmable fabric can be used to halt the CPU.

The system runs on Windows 98/NT/2000 over an IEEE1284 EPP/ECP high-speed parallel port.

The QuickMIPS SDK with the expansion connector, RTOS ports, system model, and drivers can be used as a prototype system.

The system model, SDK and the programmable logic on the QuickMIPS part allows customers to make the software and hardware tradeoffs.

Boot code in Flash memory can be downloaded through the USB port on the SDK.

Also, the Ethernet ports on the SDK allow fast downloading of code for application development.

"When we first envisioned our Codelab embedded developer suite, platforms such as the FS2 system analyser were at the forefront of our minds", said Mentor Graphics Embedded Systems Division CTO Lance Brooks.

"The combination of our hardware-assisted Codelab products, our Nucleus RTOS products, and FS2 system analyser will bring unprecedented benefits to QuickMIPS processor system developers".

"Green Hills is pleased to be part of the QuickMIPS system development platform", said Robert Redfield, director of partner programs at Green Hills.

"Software developers will greatly benefit from Green Hills' Multi 2000 optimised compilers, advanced debugger and integrated development environment when developing with the FS2 system analyser and the QuickMIPS SDK environment".

The FS2 system analyser for the QuickMIPS development system is available from First Silicon Solutions for $3995 with on-chip trace and $5995 with off-chip trace.

More information about the analyzer is available at www.fs2.com.

(This was Electronicstalk's Top Story on 9 May 2002).

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