Programmable single-chip master/target PCI bridge

The QL5632 is the latest addition to the QuickPCI family of secure, programmable master/target PCI bridge solutions.

The QL5632 is the latest addition to the QuickPCI family of secure, programmable master/target PCI (peripheral connect interface) bridge solutions from QuickLogic.

The QL5632 integrates hard-wired 32bit, 33MHz master and target PCI controllers with a configurable DMA controller, configurable FIFOs, and 200,000 gates of FPGA fabric that can be used to implement interfaces to external processors, ASICs, and FPGAs.

QuickLogic is the only IC vendor to offer PCI bridge products with on-chip FPGAs.

This new device is ideal for applications that require the transfer of data between the PCIbus and high-throughput video compression/decompression, encryption/decryption, packet processing, DMA and other data processing subsystems.

Examples of such applications include: edge routers that use multiple DMA engines for packet processing and block manipulation; T1/E1 channeliser cards that must transfer data from multiple HDLC channels to or from the PCIbus; and image processing applications in which a large FPGA or DSP may be used for video compression/decompression before sending the data to a hard drive or network.

Historically, designers of medium volume products who cannot afford the high NREs associated with masked ASICs have had two options for interfacing proprietary buses to the PCIbus: a multichip discrete solution using an ASSP and FPGA; or a stand-alone FPGA with a soft intellectual property (IP) core for the PCI controller.

Although the multichip discrete solution avoids the timing problems and verification issues associated with using soft IP, this approach requires additional board space and increases system power consumption.

On the other hand, a single-chip FPGA-based solution requires months of extra design time to develop and debug the PCI interface and resolve timing problems.

In addition, the PCIbus initialisation process must frequently be slowed down to allow enough time for an SRAM-based FPGA to be loaded and enumerated.

If bus enumeration takes place before the FPGA is loaded, the PCI controller will not be operable.

In any standard PCI plug-in card, bus initialisation cannot be slowed because it is controlled by the system BIOS.

In these cases, SRAM-based FPGA loading latency introduces the very serious risk of card inoperability.

QuickLogic's QL5632 offers the reliability, short design cycle and instant-on benefits of a fully verified, hardwired ASSP PCI controller with the flexibility of an FPGA in a high throughput single-chip solution.

QuickLogic's QL5632 programmable PCI bridge IC maintains its configuration even when the system power is off.

As there is no loading latency during system power-up, the device is always enumerated by the PCIbus.

This feature makes the QL5632 ideal for plug-in cards in systems in which the BIOS controls bus enumeration.

QuickLogic's patented ViaLink FPGA configuration technology uses vias between the various metal layers for interconnect that provide 100% routability for the QL5632 FPGA fabric.

ViaLink is a interconnect switch technology that supports field programmability, high performance and low power consumption.

As there is no external configuration EEPROM, designs cannot be reverse engineered, which means they are secure from competition cloning or copying.

With the introduction of the QL5632, QuickLogic has six programmable PCI bridge solutions, including master/target and target solutions for both 32 and 64bit PCI buses with operating frequencies of 33, 66 and 75MHz.

FPGA densities range from 50K to 200K gates in a wide variety of packages.

In addition QuickLogic offers a variety of hot swappable PCI bridge ASSPs including 32bit system master, bus master, bus target and stand-alone target for 33 and 50MHz PCI buses, with internal bus speeds ranging from 33 to 75MHz.

The QL5632 is available now in 280-pin PBGA and 208-pin PQTP packages and is priced at $21 in quantities of 25,000 units.

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