Product category:
Programmable Logic Devices
News Release from: QuickLogic | Subject: Eclipse-II
Edited by the Electronicstalk Editorial
Team on 05 February 2003
FPGAs take more functions onboard
The Eclipse-II FPGA family addresses applications that demand ultra-low power, small-form-factor packaging and high design security.
The Eclipse-II FPGA family addresses applications that demand ultra-low power, small-form-factor packaging, and high design security Eclipse-II FPGAs exceed the functionality previously addressed by complex programmable logic devices (CPLDs) and FPGA devices while providing significant power and cost savings
This article was originally published on Electronicstalk on 5 Jun 2003 at 8.00am (UK)
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With an architecture that features dedicated SRAM blocks, flexible clock architecture and ultra-low power consumption, the Eclipse-II family offers FPGA, CPLD, and ASIC designers multiple solutions for their applications.
"Our patented ViaLink interconnect technology enables QuickLogic to deliver the lowest power, most routable FPGA in the industry", said Brian Faith, Quicklogic's Manager of FPGA products.
"The low power architecture of Eclipse-II provides developers of mobile, portable, wireless, and hand-held systems with a feature-rich alternative to CPLDs and ASICs.
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In addition, the low power consumption (250mA standby current) of Eclipse-II FPGAs enables designers to reduce system costs by using smaller, less costly voltage regulators and power sources.
The Eclipse-II family is available in small form factor packaging, giving system developers the benefits of a low power, high-performance FPGA without sacrificing board space.
This packaging makes the devices ideal for miniaturised portable consumer products.
Unlike some other FPGAs, the Eclipse-II devices do not require an external memory to retain the FPGA configuration data, thereby saving additional board space and power consumption.
A single-chip solution means less board area, which in turn reduces end-system cost for designers.
Armed with QuickLogic's patented nonvolatile ViaLink interconnect technology, Eclipse-II FPGAs provide exceptionally high levels of design security from reverse engineering and IP theft.
Additional architectural features in the Eclipse-II FPGA family afford users the highest level of design security, above and beyond that of ASICs.
One of the most difficult challenges in system design today is how the multitude of clock domains are distributed and managed.
Towards this end, Eclipse-II devices are equipped with a large number of distributed clocks enabling designers to bridge up to 20 clock domains in a single Eclipse-II FPGA.
In addition, the flexible clocks networks can drive user-programmable phased locked loops (PLLs).
These PLLs can be programmed for clock frequency multiplication, division and be used to improve your design's I/O performance.
Eclipse-II PLLs not only reduce chip-to-chip delays in high performance systems, they also reduce the number of components on a designer's board, thus further reducing end-system costs.
The Eclipse-II FPGA family addresses a wide range applications such as mobile, wireless, handheld, portable, medical equipment and defined form factors such as PCMCIA, CardBus, MiniPCI and SDIO.
QuickLogic provides designers with QuickWorks, an intuitive, easy-to-use development environment including schematic entry, simulation, synthesis, accurate power calculation, timing driven placement and routing, and static timing analysis tools.
The Eclipse-II FPGA family is supported in QuickWorks Version 9.4, available now for download from the QuickLogic website.
QuickLogic offers several IP blocks for use in QuickLogic FPGAs such as PCI, memory interface, DSP and other commonly used functions.
The Eclipse-II FPGA family of devices start at $3.50 (for quantities of 250k or more).
The first device in the Eclipse II family will be sampling in Q2 2003.
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