Product category:
Design and Development Software
News Release from: QuickLogic | Subject: QuickWorks 9.6
Edited by the Electronicstalk Editorial
Team on 06 April 2004
FPGA software optimises power
consumption
Version 9.6 of the QuickWorks development software is now available and supports the QuickLogic Eclipse II family of FPGAs, the lowest power FPGAs in the marketplace.
Version 9.6 of the QuickWorks development software is now available and supports the QuickLogic Eclipse II family of FPGAs, the lowest power FPGAs in the marketplace QuickWorks V9.6 underscores QuickLogic's commitment to providing power-sensitive designers with tools specifically developed to minimise and accurately calculate the power consumption of their FPGA design
This article was originally published on Electronicstalk on 8 Jul 2008 at 8.00am (UK)
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QuickWorks 9.6 includes the revolutionary PowerAware Placer, a tool that minimises dynamic power by giving priority to power consumption during logic placement.
It also includes a sophisticated power calculator that enables accurate modelling of dynamic power consumption based on the actual place and route results.
The new power calculator also includes support for power consumption of each I/O bank of the targeted device.
"Power consumption is moving to the forefront of designers' minds, both for battery operated and heat dissipation-constrained systems," said Brian Faith, Director of Logic Products.
"As the semiconductor content of these systems continues to increase, meeting power and heat budgets proves to be increasingly challenging.
With the combination of milliwatt low power Eclipse II FPGAs and QuickWorks 9.6, designers achieve the lowest possible power consumption at the highest performance for their programmable logic design." QuickWorks V9.6 tools have also been extended to support a new design flow interface.
This easy-to-use graphical interface allows designers to access the integrated tools of QuickWorks without having to navigate menus or toolbars.
The graphical interface affords CPLD and FPGA designers new to the QuickLogic design tools an intuitive dashboard for developing and optimising their designs with QuickLogic devices.
QuickWorks V9.6 includes an ASSP Fabric Interface Wizard that automatically generates the Verilog or VHDL between the internal interface of embedded standard products (ESPs) and the designer's FPGA design.
This Wizard was designed to simplify the design flow and accelerate time to market for users of ESPs.
The basic QuickWorks V9.6 tool is available at no cost for Windows (98, 2000, Me, XP and NT).
The software can be downloaded from the QuickLogic website.
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