FPGAs further penetrate portable electronics

QuickLogic has announced an innovation in programmable logic technology, providing developers with startling new performance for portable electronics products.

QuickLogic has announced an innovation in programmable logic technology, providing developers with startling new performance for portable electronics products.

Dubbed PolarPro, the architecture moves QuickLogic's existing ultra-low-power consumption FPGA (field programmable gate array) formula to a new level, and adds further circuitry to optimise performance when implementing interfaces from deeply embedded processors to high-bandwidth peripherals such as hard disks and wireless chipsets.

The designed-for-purpose architecture means that such interfacing functions may also now be implemented at a significantly lower cost, making the solutions highly applicable for mass consumer products.

Most notably, the new FPGAs incorporate an 'instant' deep-sleep standby mode that reduces power consumption to less than 10uA.

This is up to 1000 or 10,000 times lower than Flash- or SRAM-based FPGAs respectively, and around a 25-times improvement on QuickLogic's current generation devices.

Critically, this headline power conservation level is assured in all situations, thanks to circuitry that isolates the I/O pads from the logic core when on standby.

This approach eliminates the common problem of a power drain well above an FPGA's datasheet quiescent consumption figure when it is connected to an active bus (because some quiescent modes can leave I/Os in input mode effectively, and bus traffic causes them to draw current).

In applications like this - which are commonplace in products like media players, PDAs and cellphones - an FPGA's headline static power consumption of say 100uA, might become tens of milliamps in reality.

"The functionality and power consumption demands of consumer product developers are outpacing today's silicon and battery technology", said Brian Faith of QuickLogic.

"PolarPro FPGAs provide a programmable logic solution to this mismatch that can almost be considered as a new category of silicon device, giving users the means to add non-native interfaces to deeply embedded processors, and to move power management strategies onto a completely new level".

PolarPro devices combine general-purpose FPGA logic with embedded circuitry for implementing high-bandwidth bus-to-bus interfaces, including large arrays of on-chip dual-port RAM with co-located asynchronous FIFO controllers, DDR interfaces for highly cost effective memory expansion, and clock management units.

All the circuitry is optimised for low power consumption, and supported by a new very low power mode called VLP.

VLP further optimises the low power consumption and instant-on characteristics of QuickLogic's proprietary ViaLink antifuse FPGA technology.

This special power down mode - which typically draws only 10uA - retains the state of all I/O, memory and registers yet can be entered or exited within 150us.

Ultra low power consumption is achieved partly by clever power management of the routing circuitry inside the FPGA, and allows users to implement more sophisticated and much faster power management strategies to preserve battery life.

The 10uA standby mode contrasts with quiescent current figures of around 10mA required to maintain the configuration of an equivalent FPGA based on Flash memory, or around 50 to 100mA for an SRAM FPGA.

Moreover, because of the underlying antifuse technology that controls the logic configuration of PolarPro, there are no in-rush current peaks to contend with during wake up - further reducing the cost of power circuitry.

Contrasted with a CPLD, PolarPro technology provides lower power consumption combined with memory and other dedicated circuitry that greatly reduces the component bill of materials in high-level glue logic applications such as bus-to-bus bridges.

Onchip memory, FIFO (first-in, first-out) controllers and clock management resources optimise the new devices for interfacing embedded systems processors with high-bandwidth peripherals such as wired or wireless networking chipsets, miniature hard disks, memory sticks and other storage devices.

In applications like this, programmable logic must usually bridge different system clock-frequency domains.

PolarPro's architecture addresses the overhead cost of implementing such functionality with large arrays of onchip dual-port RAM and FIFO controllers.

In the initial PolarPro release, six choices of FPGA will offer from 27 to 202kbits of embedded RAM, with an embedded asynchronous FIFO controller for every 8kbits RAM.

These FIFO controllers are sited directly adjacent to the memory for optimum speed, and include programmable 'almost empty'/'almost full' flags.

By embedding dedicated FIFO controllers throughout the architecture in this way, QuickLogic significantly reduces the effective silicon area required to implement such functions compared with the use of programmable logic cells (by an estimated 90% plus), delivering guaranteed performance asynchronous FIFOs at virtually negligible cost.

Further embedded features to assist developers with bridging clock domains come in the form of onchip configurable clock managers or CCMs.

These circuits incorporate a phase locked loop and a delay line to compensate for device-internal and/or system level interconnect delays, reducing what is often a complex debug and verification issue for FPGA users to simply setting a programmable parameter.

If further memory is required for buffering data, another key element of the new FPGAs is dedicated DDR2 (double data-rate) interfaces, allowing deeply embedded systems to use the same high speed, low cost memory devices as the latest PCs and portable computers.

Again, this feature is implemented using dedicated circuitry, located right next to the I/O pins, for maximum performance and smallest silicon area.

For this new FPGA, QuickLogic has designed the common logic cell to take advantage of the resources and cost efficiency of the latest logic-synthesis technology.

The PolarPro multiplexer-based cell supports both the industry standard 4-input look up table (LUT4) function as well as wider combinatorial functions of up to 13 inputs.

This hybrid, variable grain logic cell leverages the significant investments in logic synthesis for LUT4 FPGA architectures, as well as the traditional wide fan-in PLD architectures.

"The portable consumer product industry is evolving so fast that it's making it difficult for embedded processor vendors to provide the ideal set of peripheral interfaces".

"Over the last year for instance, QuickLogic's existing Eclipse FPGAs have been widely used for implementing bridges to MiniPCI".

"This year, demands for SDIO are becoming prevalent, and next year requests will probably include connectivity to CE ATA".

"All of these interfaces, including combinations of them, can be implemented with unprecedented economy using PolarPro", added Faith.

PolarPro will begin sampling from December.

The first member of the new family, the QL1P100 with 640 logic cells, 38k RAM, 4 FIFO controllers, and 2 configurable clock managers and up to 188 I/O pins, will be priced as low as $2.95 in volume.

QuickLogic's initial product release extends down to 480 logic cells and up to large-scale devices with 7680 logic cells and over 200k of dual-port RAM.

These high-end FPGAs provide the logic capacity and functionality to suit QuickLogic's large customer base in industrial and military-aerospace markets.

Back to top