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Product category: Programmable Logic Devices
News Release from: QuickLogic | Subject: PolarPro FPGA architecture
Edited by the Electronicstalk Editorial Team on 15 December 2005

FPGA tackles power sensitive
applications

QuickLogic's PolarPro FPGA architecture will break new ground for FPGA adoption into portable electronic applications.

QuickLogic's PolarPro FPGA architecture will break new ground for FPGA adoption into portable electronic applications Cost-effective, ultra-low power and employing small form factor packaging technology, this architecture is poised to set a new standard for enabling innovation

PolarPro supports power-conserving strategies in portable applications, while maintaining the functionality and time-to-market advantages of traditional FPGAs.

The PolarPro architecture addresses both the need to reduce power consumption and decrease system design costs through its unique embedded circuitry.

PolarPro combines FPGA logic with embedded circuitry for implementing high-bandwidth bus-to-bus interfaces, including large arrays of on-chip dual-port RAM with co-located asynchronous first-in, first-out (FIFO) controllers, DDR interfaces for highly cost effective memory expansion, and clock management units.

All device circuitry is optimised for low power usage through the new very low power mode (VLP).

The new PolarPro FPGAs incorporate an 'instant' deep-sleep VLP standby mode that reduces power consumption to less than 10uA.

This is less than 1/1000 that of flash-based FPGAs and less than 1/10,000 SRAM SRAM-based FPGAs respectively.

This power conservation level is assured in all device situations due to the dedicated circuitry that isolates the I/O pads from the logic core when in standby mode.

With the VLP mode and instant-on operation, a host processor can put the PolarPro device into and out of sleep mode in just microseconds, letting the logic hardware be efficiently controlled with a system-level interrupt scheme and saving battery power when device functionality is not needed.

This approach eliminates the common problem of device power consumption well above an FPGA's static power consumption figure when it is connected to an active bus - a common situation for processor-to-peripheral bridging implementation.

In these types of applications, which are commonplace in products like portable media players (PMPs), PDAs and cellphones, an FPGA's static power consumption of 100uA might become tens of milliamps in reality.

"Our low power ViaLink FPGA technology has allowed us to address wireless and storage connectivity challenges in portable electronics applications", said Tom Hart, QuickLogic's Chairman, President and CEO.

"Through our work with companies such as Intel, Atheros and Seagate, we have gained vital knowledge about the stringent energy resources available in today's portable products as well as their sensitivity to cost".

"We have incorporated that knowledge into the new PolarPro architecture, utilising the time-to-market advantages of FPGAs, increasing battery life and lowering the total system".

From a Consumer Electronics (CE) perspective, total product cost typically relates to the bill of materials (BOM) of a system.

The aim of QuickLogic's PolarPro architecture has been to reduce BOM cost by using the latest and lowest cost memory devices, such as mobile DDR2 memory, that leverage the high-volume markets of laptops and PCs.

In addition, with QuickLogic's ViaLink technology there is no in-rush current during power-up, such as that seen with SRAM-based FPGAs, further reducing the cost of advanced power management circuitry.

When programmable logic is used in systems with a processor, wired or wireless connectivity, and potentially nonvolatile storage such as miniature hard disks, memory sticks, and other storage devices, the logic often must bridge different system clock-frequency domains.

The PolarPro architecture addresses overhead costs with built-in FIFO controllers and other specialised circuitry.

This provides a seamless, cost-effective way to bridge several clock domains together, allowing the designer to focus on other important energy conserving strategies.

By integrating FIFO controllers into the PolarPro architecture, QuickLogic reduces the effective silicon area required to implement such functions by 97%, delivering guaranteed asynchronous FIFOs for mere pennies.

Additionally, to assist the designer with the bridging clock domains, PolarPro features advanced, low power configurable clock managers (CCMs) that compensate for any 'device internal' or 'circuit-board external' interconnect delays.

Finally, the PolarPro multiplexer-based cell supports both the industry standard 4-input look up table (LUT4) function, as well as a wider combination of functions with up to 13 inputs.

This hybrid, variable grain logic cell leverages the significant investments in logic synthesis for LUT4 FPGA architectures in addition to the traditional wide fan-in PLD architectures.

All these PolarPro innovations yield an FPGA platform that addresses the cost and stringent power consumption budgets of current and future portable electronic devices.

Version 9.8 of QuickWorks will be available for download from the QuickLogic website.

It will include timing, area and power-optimised designs for the PolarPro family suite of FPGA development tools.

The VHDL and Verilog design entry is supported by industry-leading logic synthesis tools.

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