Verification system takes in SystemVerilog

Real Intent is to add support for the SystemVerilog DAS (Design Assertion Subset) to its flagship product Verix.

Real Intent is to add support for the SystemVerilog DAS (Design Assertion Subset) to its flagship product Verix.

SystemVerilog 3.0 has been approved as an Accellera standard.

Real Intent and Co-Design Automation jointly developed the initial DAS (Design Assertion Subset) and donated it to Accellera earlier this year.

This jointly developed and donated spec is the basis for the SystemVerilog DAS.

Dr Prakash Narain, Real Intent's President and CEO said, "Real Intent is firmly behind the Accellera SystemVerilog standard.

This assertion standard enables design assertions and has significant methodology advantages over the standards being considered for testbench assertions.

We view the emergence of this standard as a rare chance for the industry to unify a diverse set of tool and methodologies and provide compelling value to customers.

Verix, our formal assertion-based verification tool, will support SystemVerilog assertions in Q3 of this year".

Verix is Real Intent's pioneering assertion-driven formal verification system that verifies that a design is free from a large class of errors early in the design cycle, prior to simulation and synthesis.

Verix features a number of formal verification innovations including: clock intent verification, automatic checks, scalable hierarchical verification, in-line assertions and automatic generation of simulation checker from formal assertions.

Verix speeds the design of high-end semiconductors and systems-on-chip by formally verifying the design as the RTL is created.

Verix pricing starts at $50,000/year.

Verix with SystemVerilog DAS assertions will ship in Q3 for Sun, HP and Linux platforms.

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