Product category:
Design and Development Software
News Release from: Real Intent | Subject: PureTime 2.0
Edited by the Electronicstalk Editorial
Team on 05 April 2007
Timing exception verifier is upgraded
PureTime removes the risk of errors in Synopsys Design Constraint timing exception verification, so designers can avoid chip respins and product introduction delays.
Real Intent has begun shipping the next generation of its formal timing exception verifier software PureTime PureTime 2.0 removes the risk of errors in Synopsys Design Constraint (SDC) timing exception verification, so that designers can avoid chip respins and electronic product introduction delays
This article was originally published on Electronicstalk on 3 Jun 2002 at 8.00am (UK)
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Its automatic timing exception processing dramatically improves project schedules when compared with a manual review of timing exceptions.
"Our customers are constantly looking for ways to improve the ROI of their engineering staff and tools expenditures".
"Verifying hundreds of lines of SDC through manual design review is error prone, extremely time consuming, and is expensive in terms of engineering time and delays to product shipments", said Rich Faris, Vice President of Marketing and Business Development at Real Intent.
"Moreover, an automatic solution is accurate, whereas manual reviews are more error prone".
PureTime 2.0 extends Real Intent's leadership position in exception verification by adding comprehensive SDC exception linting capability and the ability to verify clock domain crossing exceptions.
More capabilities new with 2.0 include the automatic export of expanded SDC, support for wildcarding in the SDC file, and enhanced algorithms for higher performance.
PureTime 2.0 offers full sequential analysis and multicycle path analysis.
Combinatorial only solutions can invalidate paths that full sequential analysis correctly identifies as valid, and can't analyse multicycle paths.
PureTime is a software timing exception verifier that detects timing exception errors that create schedule delays, chip respins or failing hardware.
Using exhaustive formal analysis, it proves the correctness of SDC false-path and multicycle path exceptions.
These exceptions can be created by designers, received as a part of intellectual property (IP), or generated by other tools.
PureTime works throughout the entire design flow, with both RTL and netlist designs.
It includes comprehensive exception linting capabilities, and is glitch and interaction aware for highest accuracy.
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