Software rises to formal verification challenges

Ascent finds bugs in RTL designs and improves design quality, with significantly higher performance compared with Real Intent's previous generation of automatic verification software.

Real Intent has begun shipping a new version of its Ascent software for automatic formal verification of electronic designs.

Ascent finds bugs in register-transfer-level (RTL) designs and improves design quality, with significantly higher performance compared with Real Intent's previous generation of automatic verification software, Implied Intent Verification.

Ascent leads design and verification engineers to important bugs, while reducing their time investment in debugging.

"Ascent delivers higher throughput and more complete checking compared with alternative solutions", says Rich Faris, Vice President of Marketing, Real Intent.

"Its analysis is more precise than syntactic checkers or lint tools, since formal analysis takes actual circuit functionality into account".

"In addition, Ascent's support for constraints and its fine grain control of reporting surpass the capabilities of competitive solutions".

Faris added: "Our customers tell us that automatic verification is of high value because it finds problems early in the design cycle, and that shortening the debugging loop has high return on investment".

Ascent automatic verification is applied early in the electronic design cycle, even before the blocks are assembled into subunits and before simulation testbenches are developed, catching many problems earlier than ever before.

It is important to catch bugs as early as possible, as the cost of an electronic design defect increases the closer you are to tape-out.

Therefore finding and fixing bugs early saves both money and time.

Ascent is a major step forward in automatic formal verification.

Its redesigned architecture is focused on automatic checks that are derived directly from the RTL design.

Ascent is the only automatic tool which supports the Property Specification Language (PSL) and SystemVerilog Assertion (SVA) constraints.

Its use of the Convergence formal engine allows the highest completion rates for checks, which translates to more bugs detected than ever before.

In addition, its reporting controls allow designers to fine tune verification reports to meet their needs.

In addition to Ascent's role in early logic verification, major design houses use it as a signoff step before RTL is checked in, thus Ascent delivers value across the entire design flow.

Ascent identifies many critical design problems: including dead code, uninitialised memory, bus contention, floating buses, and x value propagation.

Additionally, Ascent automates Finite State Machine (FSM) checks, such as unreachable FSM states, single FSM deadlock and pairwise FSM deadlock.

It can verify good design practices, when using case statements by analysing and reporting full and parallel case pragma violations.

Ascent is shipping now, was first introduced in 2006, and replaces Real Intent's Implied Intent Verification software.

The price starts at US $35,000 for a one year term licence.

Existing customers on active maintenance receive Ascent at no charge.

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