Quad-datarate SRAMs - the next generation

Renesas Technology has launched the initial phase of its 36Mbit QDR II SRAM products, the second-generation of QDR (quad datarate) SRAM.

Renesas Technology has launched the initial phase of its 36Mbit QDR II SRAM products, the second-generation of QDR (quad datarate) SRAM.

The eight new product series comprise 36 models and offer the industry's fastest operation for two-word-burst models and the maximum operating speed for four-word-burst models.

They are suitable as buffer and table memory in next-generation 10Gbit/s communication devices such as high-end routers and switches.

The new products employ a 130nm CMOS process which provides high-speed operation at a low voltage.

The two-word-burst type products, which perform burst transfer of two consecutive data words, can operate at 250MHz, whereas the four-word-burst type models, which perform burst transfer of four consecutive data words, support an operating speed of 333MHz, the maximum laid down in the QDRII specifications.

The lineup of both two- and four-word-burst models comprises wide-word x36 and x18bit products as well as x9 and x8bit products.

In addition, a range of operating frequencies is available, offering users a wide choice for their particular systems.

The products are available in 165-ball plastic FBGA (15 x 17mm) packages which offer excellent thermal radiation characteristics, are suitable for high-density mounting, and require just a small mounting area.

The QDR SRAM pin arrangement is upward compatible with products up to 288Mbit, therefore facilitating capacity upgrades.

In addition, FBGA package products support the IEEE standard test access port and boundary scan architecture (IEEE1149.1-1990) that allows interchange connection checking during module mounting to be conducted at the board level.

QDR SRAMs employ a dual-port configuration that separates input and output, enabling operation of both input and output at twice the rate of current synchronous memory.

This makes it possible transfer four data words per cycle.

For these new products an HSTL interface is used as the input/output interface.

QDRII SRAM conforms to the OC-192 (10Gbit/s) or OC-768 (40Gbit/s) next-generation high-speed optical communication standards.

The QDR specification is adapted for a JEDEC standard and is the standard for the NPF (Network Processing Forum) as the basis for LA-1 (Look-Aside Interface Phase 1).

Sample shipments of the QDRII SRAM products will begin in January 2004, with mass production commencing in Q1 2004.

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