Product category:
Memory Devices and Modules
News Release from: Renesas Technology Europe | Subject: superSRAM
Edited by the Electronicstalk Editorial
Team on 10 September 2003
Novel cell technology shrinks SRAM sizes
A novel range of low-power 16Mbit SRAM products known as superSRAMs offers the world's smallest chip size of approximately 32mm2.
A novel range of low-power 16Mbit SRAM products known as superSRAMs offers the world's smallest chip size of approximately 32mm2 This is achieved through a new memory cell technology that combines an SRAM cell using a TFT and a DRAM cell using a stacked capacitor
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
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These are suitable for use in portable devices such as mobile phones and industrial applications such as POS terminals.
The superSRAM is a new patent-pending memory cell technology that represents a complete departure from the current trend in SRAM memory cell technology.
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Using a 150nm process, the superSRAM is approximately half the size of Renesas Technology's CMOS SRAM using a conventional six-transistor structure (when employing the same process).
This will enable small sized applications with constantly increasing memory capacities to be made more compact.
The new devices also offer large capacity, low power consumption and a low soft error rate.
The new type of memory cell combines an SRAM cell that has a P-channel thin film transistor (TFT) as the load transistor and an N-channel mosfet as the driver transistor, with a DRAM cell employing a stacked capacitor at the storage node.
This capacitor enables the size of the driver transistor to be minimised, making it possible to achieve the small memory cell area.
Unlike pseudo static RAM (PSRAM) which employs DRAM cells and is used in large-capacity applications, the superSRAM does not require refreshing.
As with conventional SRAM, information stored in a memory cell is automatically maintained by means of the load transistor and driver transistor.
The use of SRAM cells employing Renesas Technology's TFT expertise provides the low power consumption essential for battery-operated portable devices, with a data retention current of 1uA at 25C.
The use of stacked capacitors, long used in DRAM cells, at memory cell storage nodes provides a structure that is extremely resistant to the occurrence of soft errors due to alpha-rays or neutron beams, making the SRAM very reliable.
Charges stored in the capacitors enable the soft error rate to be reduced by approximately two orders of magnitude compared with conventional Renesas Technology CMOS SRAM.
Two external voltage versions of the superSRAM are available on a metal mask option basis: the 1.8V (1.65 to 2.3V) R1LA1616R series and the 3V (2.7 to 3.6V) R1LV1616R series.
Each is available in two different package types: a 52-pin TSOP (10.79 x 10.49mm) with a 0.40mm pin pitch, and a 48-ball fine-pitch BGA (7.5 x 8.5mm) with a 0.75mm ball pitch.
These products will be also available in Renesas Technology's MCP form in combination with other memory devices such as Flash.
Samples will be available in November 2003.
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