Budget MCU aids Ethernet-connectable products

The SH7618 32bit SuperH RISC microprocessor features both an Ethernet controller and a host interface to facilitate connection to another microprocessor.

The SH7618 32bit SuperH RISC microprocessor features both an Ethernet controller and a host interface to facilitate connection to another microprocessor.

The new low-cost device is designed for use in applications that require a network connection capability, including industrial equipment such as factory automation and surveillance cameras, audio/video products, for example DVD recorders, and white goods such as air conditioners.

The SH7618 has a 32bit SH-2 core that offers processing performance of 130MIPS at a maximum operating frequency of 100MHz.

The on-chip Ethernet controller includes an IEEE802.3 compliant media access controller (MAC) which stipulates the frame transmission/reception method and frame format data error detection, for example.

The device also features a media independent interface (MII) for connection between the MAC layer and physical layer.

This allows direct connection to an LSI with a 10/100Mbit/s supported physical layer, simplifying the design of a high-speed Ethernet LAN connection function.

The SH7618 can be connected to another microprocessor using the host interface function, enabling the device to be recognised and controlled as an SRAM-equivalent by a main microprocessor performing system control, for example.

The host interface comprises a 16bit interface bus and two SRAM banks each with a 1Kbyte linear address space.

These are provided for direct reading and writing from the main microprocessor, enabling data downloaded via Ethernet to be transferred to the main microprocessor at high speed.

This makes it possible for basic function and network connection-related function development to be carried out in parallel during system development, enabling overall system development time to be reduced.

This also simplifies the addition of network connectivity to an existing system.

The device includes separate 256byte FIFO (first-in-first-out) memory blocks for transmission and reception and a DMAC specifically for Ethernet controller use that implements a ring buffer system.

This is a system whereby a memory area comprising a number of data buffers is configured as a ring and is controlled alternately by the CPU and DMAC.

It enables transmit/receive data to be transferred directly between on-chip memory or external memory and the Ethernet controller, making it possible to create a highly efficient network system.

The SH7618 uses a small 176-pin BGA package (13 x 13mm) which helps reduce both system cost and size.

On-chip debugging functions are included that enable real-time debugging at the maximum operating frequency, and the small PC card sized E10A can be used as an emulator.

Sample shipments of the SH7618 will begin in Europe in December 2003.

Back to top