Graphical MCU aims to control in-car information

The SH7770 SoC uses a newly developed SH-4A SuperH family CPU core and offers the industry's first on-chip 2D and 3D graphics engines for varied drawing functions, including map drawing.

The SH7770 SoC uses a newly developed SH-4A SuperH family CPU core and offers the industry's first on-chip 2D and 3D graphics engines for varied drawing functions, including map drawing.

Together with a GPS baseband processing function and more than 50 other comprehensive on-chip peripheral modules, this makes the device an ideal single-chip solution for car information systems (CIS) such as next-generation car navigation devices.

The SH-4A CPU core offers a maximum operating frequency of 400MHz, approximately 70% faster than the current SH-4 CPU core, and a high processing performance of 720MIPS.

The SH7770's cache memory employs a four-way design that provides a higher hit rate and helps speed up software processing.

The instruction set is also upward compatible with that of the existing SH-4 core, allowing existing programs to be used and system development time to be reduced.

The SH7770 incorporates most of the functions needed by a next-generation CIS, enabling a powerful and sophisticated system to be configured using a single chip.

This makes it possible to achieve lower system cost by using fewer parts, and also enables overall system power consumption to be reduced.

The on-chip 2D graphics engine offers fast and high-quality implementation of map drawing operations that are essential to car navigation systems.

A bold-line drawing function suitable for road drawing enables a line of constant width to be drawn, regardless of the drawing direction, and makes endpoint processing and painting of linked areas possible.

An anti-alias function reduces jaggedness in outline displays of polygonal areas such as parks and schools, enabling smoother outline drawing.

Such processing has previously been executed by software or dedicated LSIs, therefore providing it in hardware form in a single chip offers both faster processing and a reduction in the number of parts.

The 2D graphics engine is functionally upward compatible with Renesas Technology's current Q2SD 2D graphics engine, facilitating efficient development of a system employing the SH7770 by current Q2SD users.

The SH7770 incorporates a PowerVR MBX 3D graphics engine from UK-based Imagination Technologies.

This enables the device to handle 3D drawing not only for navigation applications but also for multimedia applications that require high-speed 3D drawing in CIS.

By processing only the visible area, unlike conventional 3D graphics engines, external memory accesses are kept to a minimum.

This enables faster, high-quality 3D drawing in full colour to be achieved without the use of external dedicated 3D graphics memory.

To further lighten the CPU load, both graphics engines also include a geometry engine that performs tasks such as vertex co-ordinate calculation.

This processing is executed at a high operating speed of 100MHz, enabling smooth, high image-quality 2D/3D graphics display operations to be implemented.

The SH7770 features over 50 on-chip peripheral modules necessary for next-generation CIS.

These include: a GPS baseband processing module, which was previously handled by a dedicated chip; an interface for connection to a speech processing IC; a USB interface for connection to a mobile phone, for example; an in-vehicle LAN CAN interface; and a variety of serial interfaces.

Other IP peripheral functions include ATAPI interface, A/D convertor and serial sound interface (SSI).

The external buses provided are a 64bit bus for connection to DDR-SDRAM and a 32bit wide extension bus for connection to Flash memory or SRAM.

The width of the SDRAM bus can also be made 32bit.

The memory controller and bus bridge include bus arbitration circuitry used to set a priority order for bus accesses by the various modules.

Four priority levels can be set, enabling external memory to be accessed efficiently by the many internal modules.

These priority level settings can be changed by the user in line with priority requirements for CPU and drawing performance.

In addition, the use of a unified memory architecture enables memory to be shared among specific modules, making it possible to reduce the number of external memory parts.

The SH7770 is available in a 520-pin BGA package (33 x 33mm).

An E10A-USB emulator connected to a host PC via a USB interface can be used as a development environment, and the provision of an on-chip debugging function enables real-time debugging to be carried out at the maximum operating frequency.

Sample shipments of the device will begin in May 2004 in Japan and other regions later, when Renesas Technology also plans to offer a reference platform that will enable users to carry out efficient system development.

The platform will feature CIS-oriented peripheral circuits that provide a user system actual-device verification environment.

It can be used as a software development tool for application software, for example, and it allows easy addition of original functions by the user.

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