Big Flash chips integrate memory management

Renesas Technology Europe has released the 512Mbit HN29V512A series of superAND Flash memory, the third phase of its superAND product range following its 128 and 256Mbit models.

Renesas Technology Europe has released the 512Mbit HN29V512A series of superAND Flash memory, the third phase of its superAND product range following its 128 and 256Mbit models.

The new series offers a fast write speed of approximately 4Mbyte/s and improved ease of use through on-chip memory management functions.

The series is available in the same small CSP package (10 x 11.5 x 1.2mm) as the current 256Mbit model.

It is suitable for use as embedded data storage memory in consumer products such as next-generation mobile phones, PDAs, handheld PCs and digital still cameras.

The new series uses a 0.13um process and Renesas Technology's AG-AND Flash memory cell technology, which offers multilevel cell technology and high speed.

This enables the fast write speed of approximately 4Mbyte/s.

Two 3.3V power supply voltage models are available, the x16bit configuration HN29V512A0A, supporting a 16bit bus width, and the x8bit configuration HN29V512A1A, supporting an 8bit bus width.

A 1.8V version is also under development to meet the demand for lower-voltage operation.

The built-in memory-management functions, such as bad-sector management, wear levelling and error correction, have been optimised for on-chip use based on experience gained from the development of controllers for Flash cards such as CompactFlash and MultiMediaCards.

These complex functions simplify system design and reduce the design workload because previously they would have been handled on the system side when AND Flash memory is embedded into an end product.

The bad-sector management function enables the Flash memory to detect if an abnormality occurs in a certain sector during rewriting and automatically switch to a spare sector.

In this way, the chip itself achieves 100% perfect operation throughout its lifetime, regardless of whether a defect is present when the chip is shipped or occurs after shipment, enabling system design to be completed in a short period.

The wear levelling function enables effective use of Flash memory rewrite areas and extends Flash life.

If write operations are concentrated locally, the chip becomes susceptible to damage.

Therefore, when rewrite operation reaches a predetermined number of times, the function automatically switches data and addresses to an area in which few rewrites have been performed.

The error correction function provides data reliability and enables the design workload to be reduced on the system side.

It enables the memory to detect if read data differs from written data when data is read, identify the location at which the change occurred and correct it.

The device also offers an 8Kbyte power-on auto-read function (boot function).

When power is turned on, data reading is possible by controlling two control lines (the CE pin and RE pin) even without command or address input.

Sample shipments of the 3.3V HN29V512A0A and HN29V512A1A will begin in May 2004 in Europe.

Sample shipments of the 1.8V device are scheduled for Q3 2004.

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