Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: Renesas Technology Europe | Subject: Five-layer stacked SiP
Edited by the Electronicstalk Editorial
Team on 15 April 2004
Five-layer package takes in MCU, logic
and memory
A novel five-layer stacked SiP (system in package) device combines a high-performance SuperH microprocessor, logic LSI chip and memory chips in a single package.
A novel five-layer stacked SiP (system in package) device combines a high-performance SuperH microprocessor, logic LSI chip and memory chips in a single package This new product increases the current maximum number of stacked chips in an SiP from three to five, offering users a wider choice of chip combinations while enabling the mounting area to be reduced by approximately 70 to 80% (Renesas Technology comparison)
This article was originally published on Electronicstalk on 26 May 2003 at 8.00am (UK)
Related stories
Microcontroller shinks to metering applications
The H8/38004F MCU offers extremely low power consumption together with 32Kbyte single-supply on-chip Flash memory and is the first in the SLP series that is available in a 64-pin quad flatpack.
Platform speeds SH-3 applications development
The EDOSK7705 is a low-cost high-integration OS reference platform for the SH7705 32bit microprocessor.
The device is ideal for digital consumer products, such as digital video and still cameras, PDAs and mobile phones.
The five-layer stacked SiP enables greater flexibility in creating a suitable configuration for a particular system.
The stack structure enables the mounting area to be reduced compared with the use of individual packages, making it possible to create more compact systems.
The device can also reduce system development times and can help users bring new systems to market in the shortest possible time.
Using existing chips, the SiP can be developed in approximately five to six weeks from final specification to sample delivery.
The SiP offers reduced EMI noise and therefore stable high-speed operation.
This is because housing a number of chips in a single package dramatically decreases the length of wiring between chips.
The device also simplifies system board design, and therefore reduces system development time, because the wiring of high-speed operation sections, such as the interface between the microprocessor and memory, is processed within the SiP.
The user's bus design is therefore not necessary.
Renesas Technology currently mass-produces flat-type SiPs and two- and three-layer stacked SiPs incorporating microcomputer chips such as a SuperH microprocessors, M16C or M32C microcontrollers and memory, such as synchronous DRAM or Flash memory, in a single package.
It is pursuing the development of SiPs as part of its SIP (solution integrated product) offering to users.
Orders for the five-layer stacked SiP will be accepted from April 2004.
• Renesas Technology Europe: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
