Upgraded core to power real-world SoCs

The SH-2A is a new 32bit RISC CPU core for use in control devices in the automotive, industrial and consumer fields.

The SH-2A is a new 32bit RISC CPU core for use in control devices in the automotive, industrial and consumer fields.

The SH-2A is the successor of the SuperH RISC microprocessor SH-2 CPU core, and offers a major increase in performance together with improved program code efficiency.

The SH-2A is designed for products requiring real-time capability, and is ideal for use in single-chip microcontrollers and SoCs in automotive engine control systems, consumer and industrial products such as printers and AC servos.

Automotive engine control has become more complex with the recent emphasis on environmental conservation and improved fuel consumption, while at the same time there is a trend toward the development of large-scale systems in short time frames through the adoption of autocode technology driven by improvements in development tools.

The field of industrial products such as AC servos is also witnessing advances in system precision, while more and more consumer products such as printers are appearing in the form of multifunction systems.

For example, there is a demand for faster processing providing coupled printing control while executing high-speed computational operations on image data from a DSC or scanner, and control systems in these fields require microcontrollers that offer high speed, high performance, and large-capacity on-chip Flash memory.

Against this backdrop, Renesas Technology has to date released single-chip microcontrollers for these markets featuring an SH-2 32bit RISC CPU core with an operating frequency range of 50 to 80MHz, together with embedded fast, large-capacity Flash memory, on-chip peripheral functions including a 16bit PWM timer, CAN and A/D convertors etc, which are already widely used.

Now, in response to the need for even higher speed and performance, Renesas Technology and Hitachi have jointly developed the new SH-2A RISC CPU core as an upward-compatible version of the SH-2.

Features and details of the SH-2A are as follows.

Use of a superscalar architecture enables up to two instructions to be executed simultaneously.

In addition, a Harvard architecture is employed that uses separate buses for data and instructions, preventing contention between instruction fetches and data accesses.

As a result, performance does not degrade when executing operations involving consecutive memory accesses.

The current SH-2 has a processing performance of 104MIPS at the maximum operating frequency of 80MHz, whereas the SH-2A achieves processing performance of 360MIPS at 200MHz - an approximately 3.5-fold improvement.

Processing performance per megahertz unit frequency has been improved approximately 1.4-fold, from 1.3 to 1.8MIPS, through the use of a superscalar architecture.

In other words, an approximate 40% improvement in performance is achieved at the same operating frequency, and a lower operating frequency is required to achieve the same performance, enabling system power consumption to be reduced.

The instruction set of the SH-2A is upward compatible with that of the SH-2.

New 32bit instructions and addressing modes have been added to the previous 16bit instructions, and a total of 112 instructions are now supported, including 21 FPU (floating-point processing unit) related instructions.

Addressing modes using 32bit instructions enable program address information etc to be embedded in the instruction code, making it possible for a larger area to be accessed by a single instruction.

This enables program code to be made smaller than in the case where address information is stored in memory in table form, as at present, reducing the necessary memory capacity and so helping to cut system costs.

In addition, the SH-2A supports the following instructions offering improved real-time control performance and code efficiency: bit-operation instructions that improve real-time performance; instructions offering faster, single-instruction implementation of 32bit data division; barrel-shift instructions enabling shifting of any number of bits; and store-multi/load-multi instructions enabling single-instruction coding of stack save/restore operations for CPU general registers required in the event of a subroutine call.

The instruction set is upward-compatible with that of the SH-2, enabling programs developed for the SH-2 to be used as a further aid to reducing system development time.

Normally, when an interrupt event occurs, CPU internal register information at that point is stored in stack memory by software processing before execution of the application program for the interrupt event is started.

The SH-2A incorporates special-purpose registers for storing CPU internal register information.

The CPU and special-purpose registers are connected via a dedicated bus, and when an interrupt event occurs, CPU internal register information is stored in the special-purpose registers at high speed by hardware.

As a result, the time between the occurrence of an interrupt event and the actual start of application program execution has been cut from a minimum of 37 cycles in the SH-2 to six cycles in the SH-2A.

This enables fast application program switching to be implemented, making it possible to achieve high-quality real-time control with better responsiveness.

Development tool plans include the development of an SH-2A C/C++ compiler, and support of the compact E10A-USB, and the E200F incorporating a real-time profiler function, as emulators.

Renesas Technology plans to release an initial-phase product incorporating the SH-2A by the third quarter of 2004, and to continue with subsequent phased releases.

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