Triple-bus design speeds multimedia MPU

The SH7780 microprocessor combines the high-end SuperH SH-4A CPU core with a PCIbus controller.

The SH7780 microprocessor combines the high-end SuperH SH-4A CPU core with a PCIbus controller.

The device features a dedicated triple-bus architecture and delivers 720MIPS and 2.8GFLOPS at 400MHz - a combination that provides an overall improvement in system performance.

For example, the SH7780 supports sophisticated speech recognition and speech synthesis without the need for external DSP.

The microprocessor is designed for high-performance multimedia applications such as car navigation systems, game machines and digital home electronics products.

The SH7780 employs three dedicated external busses: a 32bit double-datarate SDRAM bus at 160MHz (DDR-SDRAM320); a 32bit bus for PCIbus connections; and a 32bit local bus at 100MHz for connecting to Flash memory, SRAM, ATAPI and PCMCIA.

These are connected via an internal SuperHyway 64bit "router type" bus.

Furthermore, the three external buses can be operated simultaneously, allowing for efficient data transfer and improved performance.

This architecture allows fast boot-up time when transferring data from Flash memory to DDR-SDRAM.

The result is an overall enhancement in system performance.

In addition, the SH7780 incorporates an on-chip floating-point unit (FPU) with a maximum operating speed of 400MHz.

The FPU supports both single-precision and double-precision arithmetic operations and delivers a maximum processing performance of 2.8GFLOPS when operating in single-precision mode.

Hardware support for sine/cosine arithmetic operations also contributes to high-speed rendering of 3D graphics and DSP calculations.

The four-way set-associative cache memory is divided into two 32Kbyte areas - one for instructions and one for data.

This results in an improved cache hit ratio in comparison with existing products based on the SH-4 core.

The SH7780 also offers 16Kbyte on-chip high-speed RAM for real-time performance, to store exception handling routines, for example.

The SH7780 incorporates an on-chip PCIbus controller (PCIC).

This makes it possible to connect the microprocessor to a PCIbus, the type of general-purpose bus commonly used in PCs.

Moreover, the PCIC supports the PCI Rev 2.2, allowing connections with LSI devices incorporating a PCI interface and operating at either 66 or 33MHz.

This makes it easy to make connections with graphic chipsets or low-cost external devices such as PC peripherals.

The instruction set from the new SH-4A core is fully SH-4 upward compatible.

This makes it possible to use existing programs and helps reduce system development time.

Sample shipments of the SH7780 will begin in November 2004.

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