Nonvolatile memory uses technology from hard disks

Renesas Technology has developed a high-speed, high-reliability MRAM (magnetoresistive random access memory) technology for SoC use.

Renesas Technology has developed a high-speed, high-reliability MRAM (magnetoresistive random access memory) technology for SoC use.

Using this technology, the company has fabricated a prototype 1Mbit MRAM employing a 130nm CMOS process.

Investigation showed the prospect of high-speed operation with an operating frequency of 143MHz or above at a 1.2V operating voltage, and measurements in a one-trillion-rewrites experiment confirmed that there was no degradation.

Renesas Technology achieved these results through joint research with Mitsubishi Electric Corp and announced them this week at the 2004 IEEE International Electron Device Meeting in San Francisco.

The functions and performance of mobile devices and digital consumer appliances have improved remarkably in recent years, and this trend will continue in the future.

As higher performance and functionality and lower power consumption are required in product development, there is a demand for technologies that will make this possible.

Memory elements used for data storage and others play an important role as a key technology supporting higher product functionality and performance, and various types of memory elements have been developed to date.

To meet future needs, efforts are being made to improve various kinds of conventional volatile and nonvolatile memory elements on the one hand, at the same time as research is being conducted into new types of next-generation memory offering novel characteristics.

One such new kind of memory, MRAM, is a nonvolatile memory that enables data to be retained when power is cut while also providing high-speed operation capability.

This ability to implement functions provided by various kinds of conventional memory has led to high expectations of MRAM as next-generation memory.

MRAM stores data by using magnetic material often used in hard disk read magnetic heads, and an MTJ (magnetic tunnel junction), which comprises a tunnel layer.

Its performance depends on the composition and structure of this MTJ.

The joint development team looked at the relationship between the magnetoresistance (MR) ratio and resistance area (RA) in the MTJ, and by further applying correlativity with read speed, the team established an original method of finding the optimal conditions for achieving high speed.

This optimisation method was developed ahead of other manufacturers, and was established by making clear the universal relationship that exists between electrical resistance and the magnetoresistance ratio.

Use of this method makes it possible to determine the best combination of electrical resistance and magnetoresistance ratio.

The MTJ structure comprises a free layer, tunnel layer and pin layer.

With conventional Renesas MRAM, CoFe (ferrocobalt: magnetic material), AlOx (alumina), and CoFe are used, respectively, and high-speed operation with an operating frequency exceeding 100MHz has been confirmed in trial production.

In order to attain still higher speed, it is necessary to achieve a higher magnetoresistance ratio, but investigation with the optimisation method showed that it is difficult to improve the magnetoresistance ratio with CoFe.

For this reason, the following techniques were studied and applied in order to achieve higher speed.

With the above optimisation method, material-related studies can be conducted simultaneously.

As a result, it was found at the same time that CoFeB rather than CoFe is suitable for realising a magnetoresistance ratio that enables high-speed operation.

As predicted by the optimisation method, the use of CoFeB improved the magnetoresistance ratio by approximately 30 to 70%.

Although simply changing the magnetic material to CoFeB increases the magnetoresistance ratio, electrical resistance also increases, and higher speed cannot be achieved.

On the other hand, electrical resistance can be lowered by making the tunnel layer thinner, although an excessively thin tunnel layer leads to reliability problems.

Using the present optimisation method, the development team found the right tunnel layer thickness that enables both high speed and reliability.

This has made it possible to realise a high magnetoresistance ratio and low electrical resistance at the same time.

Use of the above approach gives a cell sensing time (data read time) of 5.2ns, presenting the prospect of achieving a read cycle of approximately 7ns and an operating frequency in excess of 143MHz.

Furthermore, an experiment in which one trillion write cycles were executed in a high-temperature environment of 150C showed almost no degradation.

This confirmed that high reliability can be achieved despite reducing the thickness of the tunnel layer.

Using the technology, a prototype MRAM was fabricated using four-layer copper wiring, and its effects were studied.

Using a 1T-1MTJ structure comprising one transistor and one MTJ for the memory cells, a TMR (tunnel magnetoresistance) element sise of 0.26-0.44um2 and the worlds smallest memory cell size of 0.81um2 have been achieved.

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