Soft error immunity improved in CAM devices

Renesas Technology Corp has introduced technology that improves soft error immunity in content addressable memory (CAM) devices used in networking and communication equipment, and similar products.

Renesas Technology Corp has introduced technology that significantly improves soft error immunity in content addressable memory (CAM) devices used in networking and communication equipment, and similar products.

The new technology addresses a critical market requirement for soft error countermeasures, particularly for systems that must demonstrate high reliability, driven by the industry-wide trend to move to finer semiconductor manufacturing process nodes.

Renesas engineers revealed details of the high reliability CAM technology in a paper presented at the 2005 IEEE Custom Integrated Circuits Conference (CICC) in San Jose, California, USA, on 20th September 2005.

As a result of this technology, data from a 144Kbit ternary-CAM (TCAM) test chip, incorporating the technology and fabricated in a 130 nm CMOS process, confirmed an improvement in soft error immunity of approximately six digits compared with chips without it.

The new TCAM technology achieves a significant improvement in reliability without degrading search and routing times.

In developing the new technology, Renesas engineers wanted to use error checking and correction (ECC) circuitry.

To do so, however, they had to triumph over the fact that ECC is based on read operations, yet the majority of operations in CAM are searches, and read operations only occur sometimes.

Moreover, the engineers could not use the traditional method for increasing noise immunity (increasing storage node capacitor capacity and accumulated charge) because in CAM cells, storage node capacitor capacity and accumulated charge decrease as structural processes become finer.

The high reliability CAM technology invented by the Renesas development team overcomes both of these obstacles.

To dramatically improve soft error immunity, the technology uses three main elements.

It incorporates embedded DRAM with ECC into the CAM device.

It provides a test circuit that efficiently measures the CAM soft error rate during a search.

It adds circuits that automate CAM data maintenance operations.

The embedded DRAM portion of the chip is basically used to store a copy of the data in the CAM portion.

When a search operation is performed in the CAM, refresh operations occur periodically in the DRAM portion.

During each refresh cycle, the ECC corrects erroneous DRAM data caused by soft errors copied from the CAM portion.

Thus, subsequent data rewrites from the DRAM into the CAM do not contain the soft errors.

This enables a high degree of reliability for data stored in the CAM portion of the device.

The test circuit used in the technology performs mass multi-bit testing of CAM cells arranged in one column using a search operation.

The circuit quickly and efficiently detects whether or not there is an incorrect bit due to a soft error in the data in CAM portion of the device.

The circuits added to automate CAM data-maintenance operations eliminate the need for halting a search operation to perform routine required functions such as adding or deleting data stored in the CAM, then making the associated data rearrangements.

The new technology carries out the requisite data maintenance operations in the DRAM portion of the chip then rapidly transfers the maintenance results back into the CAM.

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