Product category:
Memory Devices and Modules
News Release from: Renesas Technology Europe | Subject: TTRAM
Edited by the Electronicstalk Editorial
Team on 27 September 2005
Twin-transistor RAM has no capacitors
A novel high density capacitorless twin-transistor RAM (TTRAM) achieves both high speed operation and low power consumption.
Renesas Technology has developed a high density capacitorless twin-transistor RAM (TTRAM) that achieves both high speed operation and low power consumption Researchers from Renesas unveiled details of the TTRAM in a paper presented at the 2005 IEEE Custom Integrated Circuits Conference (CICC) in San Jose, California
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
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In a 2Mbit test chip fabricated with a 130nm SOI CMOS process, the TTRAM has achieved 250MHz operation in continuous data output mode and 133MHz in random access operation, while dissipating an active power of only 148mW, nearly 43% less than a conventional Renesas 130nm CMOS process embedded DRAM.
Whereas a DRAM cell requires a specially shaped capacitor, the TTRAM memory cell doesn't use a capacitor, and so is compatible with shrinks of process technology that make transistors smaller and faster.
Thus, TTRAM has a clear technology roadmap for current and future manufacturing techniques.
Also, on the 2Mbit test chip, the TTRAM cell size is 0.33um2, over 5% smaller than the 0.35um2 cell size of a 130nm CMOS process embedded DRAM test chip fabricated separately by Renesas.
In the new TTRAM memory cell, two transistors are serially connected on an SOI substrate.
One is an access transistor, while the other is used as a storage transistor and fulfils the same function as the capacitor in a conventional DRAM cell.
Data reads and writes are performed according to the conduction state of the access transistor and the floating-body potential state of the storage transistor.
The fact that TTRAM memory cell operations don't require a step-up voltage or negative voltage, as DRAM cells do, makes the new cell design suitable for use with future finer processes and lower operating voltages.
With the Renesas TTRAM, a read signal from a memory cell appears as a difference in the transistor on-current.
A current-mirror type sense amplifier detects this difference at high speed, using a reference memory cell that allows reliable identification of the 0 and 1 data levels.
This reading method significantly decreases power consumption by eliminating the charging and discharging of bit lines, operations required for reading DRAM memory cells.
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