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Product category: Microprocessors, Microcontrollers and DSPs
News Release from: Renesas Technology Europe | Subject: RS-4 16bit secure MCUs
Edited by the Electronicstalk Editorial Team on 13 November 2007

MCUs provide credit card security

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The RS-4 series maintains CPU instruction code compatibility with its predecessor while delivering approximately five times the processing performance.

Renesas Technology Europe has released the RS-4 series of 16bit secure MCUs for smart card applications in fields requiring a high level of security, such as credit or debit cards issued by banks or finance companies and ID cards The RS-4 series can deliver five times the processing performance of previous Renesas products of this type

The RS-4 series of 16bit secure MCUs is the successor to the AE-4 series of 16bit secure MCUs.

The RS-4 series maintains CPU instruction code compatibility with its predecessor while delivering approximately five times the processing performance.

This increased processing power enables the RS-4 series to handle tasks that were beyond the AE-4 series and would previously have required developers to employ a 32bit Renesas MCU.

The new secure MCUs can perform complex processing at high speed, making it possible for them to run a multiapplication OS (such as Java Card or MULTOS) faster, which is necessary to implement multiple functions on a single smart card.

In addition, the low-power design makes it suitable for noncontact type operation.

The RS-4 series enables developers to realise contact-type or noncontact type smart cards offering high-performance and multifunctionality using a 16bit MCU.

The RS-4 series implements encryption processing, required in the financial field, based on that of the AE-4 series.

In addition, the RS-4 series adds a coprocessor supporting stronger AES (Advanced Encryption Standard) encryption and other security features.

The final product versions will offer smart card MCU security level EAL5+5 certification as defined under the latest version of the Common Criteria for IT Security Evaluation.

The RS-4 CPU core of the new RS-4 series employs a Renesas architecture that has been developed for use in secure MCUs.

It has a 16bit arithmetic unit and a 16bit internal bus.

The RS-4 CPU core supports the entire instruction set of the earlier Renesas AE-4 16bit CPU core for code-level compatibility.

This means that software resources developed for the AE-4 series can be re-used with the RS-4 series, reducing the time and cost required for system development.

Compared with the AE-4 series, the RS-4 series is designed to deliver better performance, enhanced security and additional peripheral functions for improved flexibility.

The minimum time required by the RS-4 16bit CPU to execute one instruction is one clock cycle.

Compared with the earlier AE-4 16bit CPU, which needs two cycles per instruction, the RS-4 series is twice as fast when operating at the same clock frequency.

Furthermore, the RS-4 is not dependent on an external clock by having an internal clock oscillator as one of its new peripheral functions and achieves the maximum internal operating frequency of 20MHz.

The overall result of these improvements is approximately five times the processing performance of the AE-4 series.

This extra power enables the RS-4 series to handle the complex processing load of a multiapplication OS such as Java Card or MULTOS faster.

The low power design of the RS-4 series makes it suitable for use in noncontact type smart cards, which the 32bit AE-5 series does not support.

The RS-4 series can be used in both contact and contactless smart cards.

The encryption processing functions of the new RS-4 series are implemented by a powerful modular multiplication coprocessor supporting RSA encryption and a triple DES (data encryption standard) coprocessor that improves on the previous DES coprocessor.

There is also a new coprocessor with support for AES, an encryption standard that is gaining attention as a successor to DES.

The RS-4 series can process a variety of types of encryption operations at high speed.

Other peripheral functions that contribute to enhanced security include: a new pseudo-random sequence generator for generating random numbers at high speed as an effective security measure; and incorporation of the latest security technology for protecting against light attacks.

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