Multicore processors aim for automotive multimedia

Each device incorporates two Renesas Technology SH-4A high-performance CPU cores to achieve superior processing power of up to 1920MIPS.

Newly developed by Renesas Technology, the SH7786 group of dual-core processors are built around twin SH-4A CPU cores.

The SH7786 group is intended for high-performance multimedia systems, especially car information systems (CIS) such as car navigation systems.

Each device incorporates two Renesas Technology SH-4A high-performance CPU cores to achieve superior processing power of up to 1920MIPS (when operating at 533MHz).

Samples of the first product version, fabricated using a 90nm process, are currently being shipped to selected automotive customers.

The second product version, fabricated using a 65nm process, is under development.

The 65nm version, based on the 90nm version, will provide reduced power consumption and an enhanced cost to performance ratio.

Sample shipments will begin in October 2008 in Japan.

The device will be made available to Renesas Technology's wide base of consumer and industrial customers in 2009.

For its two CPU cores the SH7786 group uses the well-established SH-4A, the most powerful CPU core available in the SuperH family of 32bit RISC microcomputers, and a newly adopted core architecture that supports a dual-core configuration.

The SH7786 group supports both symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP) allowing both CPU cores to handle a single processing task using parallel processing for improved efficiency.

This results in a maximum processing performance of 1920MIPS (at 533MHz).

The SH7786 group can handle the high-speed processing of complex data necessary to meet the requirements of next-generation car navigation systems with functions such as graphical display capabilities, high-quality audio reproduction, and image recognition, while also reducing power consumption.

Another major feature of the SH7786 group is simplified system development of multicore products.

When developing a multicore product, separate systems (domains) with different characteristics and functions are allotted to each CPU core, and a distributed function system design is used so the CPU cores can interoperate and function in an integrated manner.

The SH7786 group employs technologies developed by Renesas Technology that support the building of a distributed function system (communication interface technology for interoperability between the operating systems of multiple domains and technology for preventing interference between these operating systems).

This enables developers to make use of existing software resources designed for single operating systems and makes it possible to build a multicore distributed function system in a short amount of time.

These technologies also support the running of different operating systems simultaneously with a high level of reliability.

In future Renesas Technology plans to develop additional multicore products based on this technology, including processors with four CPU cores and dual-core system on chip (SoC) products implementing most of the functions required by car navigation systems, such as image processing.

The SH7786 group integrates dual SH-4A CPU cores on a single chip.

The SH-4A is a 32bit RISC CPU core consisting of a CPU and FPU that are backward compatible at the instruction set level with SH-1, SH-2, SH-3 and SH-4 microcomputers from Renesas Technology.

This dual SH-4A CPU cores configuration can be used in a core architecture that supports a dual-core configuration, and the dual cores support both symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP), providing developers with plenty of flexibility when building systems.

The clock frequency and low-power mode can be set independently for each CPU, making it possible to minimise power consumption while responding to changes in the processing load.

The SH7786 group incorporates dual SH-4A CPU cores, each with a processing performance of 960MIPS at 533MHz, and achieves a maximum processing performance of 1920MIPS.

It can handle the high-speed processing of complex data necessary to meet the requirements of next-generation car navigation systems with functions such as graphical display capabilities, high-quality audio reproduction, and image recognition, while also reducing power consumption.

Each CPU core has a built-in floating-point processing unit (FPU) with a maximum operating frequency of 533MHz.

These FPUs support both single-precision and double-precision arithmetic operations and achieve a maximum single-precision performance of 7.46GFLOPS.

This is ideal for high-speed and high-quality codec processing of still images or MPEG video.

Rapid development of distributed function systems employing multi-core technology and support for highly reliable operation In a distributed function system using a multicore device, the individual subsystems having different characteristics and functions are called domains.

The SH7786 group employs Exreal-Exaria, a communication interface (domain interoperation) technology for integrating the operating systems of multiple domains, and Exreal-Exvisor, a technology for preventing interference between the operating systems of multiple domains.

These two technologies help simplify the development of distributed function systems using multicore devices.

They make it possible to use existing software resources originally developed for use with a single SH-4A CPU core in systems built around a SH7786 group dual-core processor, thereby shortening the time needed for development.

They also make it possible to run multiple OSs with a high level of reliability.

real-time trace-back support for reduced software development load During system development, the customer goes through a process called debugging to eliminate software bugs.

This involves checking traces to determine whether or not the software executed properly on the installed processor.

The SH7786 group dual-core processor includes H-UDI (user debug interface) and AUD (advanced user debugger) on-chip debugging functions.

They support real-time debug and trace at the processor's maximum operating frequency.

Additional products such as emulators enable flexible debugging and ease the burden of software development for the customer.

On-chip PCI Express bus interfaces for high-speed data transfer The PCI Express is a serial I/O bus interface that supports large-volume data transfers.

The SH7786 group implements multiple PCI Express bus interfaces that can be set to operate as one to four lanes, enabling high-speed data transfer at up to 800Mbyte/s with external memory or other devices equipped with multiple PCI Express bus interfaces.

There is also a high-speed data transfer function between lanes.

For example, it is possible to realise high-level display capabilities by connecting a high-performance external display device conforming to the PCI Express bus connection specification.

In addition, existing inexpensive and standardised peripheral devices can be used so long as they support the PCI Express bus interface.

This allows for flexible expansion and helps to reduce the overall system cost.

The dual SH-4A CPU cores of SH7786 Group support both symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP).

For SMP it implements a snoop controller, which maintains the coherency of the internal caches of the CPUs by handling exchanges of cache update data between the CPU cores.

In addition, the clock frequency and low-power mode can be set independently for each CPU, making it possible to minimise power consumption while responding to changes in the processing load.

Each CPU core has internal cache memory configured as a 32Kbyte four-way set associative instruction cache and a 32Kbyte four-way set associative data cache.

Cache coherency support enables high-speed software processing.

Furthermore, each CPU has 8Kbyte of RAM for high-speed instruction fetches and 16Kbyte of RAM for high-speed data access.

The real-time performance of the system can be enhanced overall by storing exception handling routines in these RAM areas.

In addition to the PCI Express bus interfaces mentioned above, the SH7786 group implements USB 2.0 high-speed (480Mbit/s) host and function support.

This simplifies the development of systems with USB functionality and eliminates the need for a dedicated external USB 2.0 controller.

The SH7786 group also integrates a media access controller (MAC) conforming to the IEEE802.3 standard.

This makes it easy to implement functionality for connecting to a 10/100Mbit/s Ethernet LAN.

Development environment options include the E10A-USB supplying multicore on-chip debugging emulator, which offers a range of flexible simultaneous and single-CPU debugging functions including simultaneous execution, simultaneous break, and single-CPU break and re-execute.

Moreover, E200F full-spec emulator supplying multicore offers a multicore trace functions.

They reduce the workload of the software developer when using the development environment.

With the SH7786 group as a basis, Renesas Technology will continue to develop advanced peripheral functions for a variety of fields and to release new products that meet the evolving demands of the market.

Typical applications are car navigation systems, game consoles, digital home electronics, industrial equipment etc.

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