Dual-core processor powers up to 1920MIPS

The new SH7786 incorporates dual SH-4A high-performance 32bit RISC CPU cores, each with a processing performance of 960MIPS at 533MHz.

Renesas Technology Europe has announced a new SH7786 dual-core processor fabricated with a 65nm process for high-performance multimedia equipment such as car navigation systems.

It realises excellent processing performance of up to 1920MIPS at 533MHz and ultra-high-speed data transfers.

The device will be made available to Renesas' wide base of consumer and industrial customers in 2009.

Renesas already developed the SH7786 dual-core processor fabricated with a 90nm process achieving the same processing performance with that of a 65nm process product.

However, the 65nm process version realises lower power consumption by finer process and ultra-high-speed data transfer by incorporating DDR3-SDRAM memory interface.

The new SH7786 incorporates dual SH-4A high-performance 32bit RISC CPU cores, each with a processing performance of 960MIPS at 533MHz, and achieves a maximum processing performance of 1920MIPS.

It can handle the high-speed processing of complex data necessary to meet the requirements of next-generation car navigation systems with functions such as graphical display capabilities, high-quality audio reproduction, and image recognition.

In addition, the 65nm process enables lower power consumption and lower heat generation.

There are also three low-power modes that can be specified independently for the two CPU cores, further reducing power consumption.

The new SH7786 integrates a dedicated 32bit bus operating at 533MHz for connecting to high-speed DDR3-SDRAM, enabling ultra-high-speed data transfer at up to 4.27Gbyte/s.

In addition, multiple PCI Express bus interfaces supporting large-volume data transfer provide high-speed data throughput at up to 800Mbyte/s.

This makes it possible to implement sophisticated drawing such as smooth of complex and real 3D graphics.

Earlier 90 nm SH7786 products were compatible with DDR2-SDRAM with an operating voltage of 1.8V.

The new 65nm versions support DDR3-SDRAM with an operating voltage of 1.5V, allowing a further reduction in the power consumption of the overall system.

A version of the E10A-USB on-chip debugging emulator with multicore support is available as a development environment for the SH7786.

It provides a range of flexible simultaneous debugging functions including simultaneous execution, simultaneous break, and single-CPU break and re-execute.

The new SH7786 is fully supported by QNX Neutrino RTOS and the QNX Momentics development suite.

The SH7786 with dual SH-4A CPU cores supports both symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP).

For SMP it implements a snoop controller, which maintains the coherency of the internal caches of the CPUs by handling exchanges of cache update data between the CPU cores.

In addition, the clock frequency and low-power mode (total of four available) can be set independently for each CPU.

For example, one CPU core can continue to operate while the other is set to one of the low-power modes to reduce power consumption.

This makes it possible to minimise power usage while responding to changes in the processing load.

Each CPU core has a built-in floating-point processing unit (FPU) with a maximum operating frequency of 533MHz.

These FPUs support both single-precision and double-precision arithmetic operations and achieve a maximum single-precision performance of 7.46GFLOPS.

This is ideal for high-speed and high-quality codec processing of still images or MPEG video.

Each CPU core has internal cache memory configured as a 32Kbyte four-way set associative instruction cache and a 32Kbyte four-way set associative data cache.

Cache coherency support enables high-speed software processing.

Furthermore, each CPU has 8Kbyte of RAM for high-speed instruction fetches and 16Kbyte of RAM for high-speed data access.

The real-time performance of the system can be enhanced overall by storing exception handling routines in these RAM areas.

The SH7786 implements three PCI Express bus interfaces that can be set to operate as one to four lanes, enabling high-speed data transfer at up to 800Mbyte/s with external memory or other devices equipped with multiple PCI Express bus interfaces.

There is also a high-speed data transfer function between lanes.

For example, it is possible to realise high-level display capabilities by connecting a high-performance external display device conforming to the PCI Express bus connection specification.

In addition, existing inexpensive and standardised peripheral devices can be used so long as they support the PCI Express bus interface.

This allows for flexible expansion and helps to reduce the overall system cost.

Regarding the development environment, the SH7786 employs technologies developed by Renesas Technology that support the building of a distributed function system that will be available in early 2010.

When developing a multicore product, separate systems (domains) with different characteristics and functions are allotted to each CPU core, and a distributed function system design is used so the CPU cores can interoperate and function in an integrated manner.

The SH7786 employs technologies developed by Renesas Technology that support the building of a distributed function system (communication interface technology for interoperability between the operating systems of multiple domains and technology for preventing interference between these operating systems).

This enables developers to make use of existing software resources designed for single operating systems and makes it possible to build a multi-core distributed function system in a short amount of time.

These technologies also support the running of different operating systems simultaneously with a high level of reliability.

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