Product category:
Intellectual Property Cores
News Release from: RF Engines | Subject: Matrix
Edited by the Electronicstalk Editorial
Team on 23 June 2004
IP provides precise FFT solutions
A novel range of "building blocks" for digital transceiver designs offers a "mix-and-match" route to precisely tailored FFT solutions that maximise silicon efficiency.
The Matrix range of high-specification "building blocks" for digital transceiver designs offers a unique "mix-and-match" way to create precisely tailored FFT solutions that maximise silicon efficiency The building blocks are supplied as intellectual property (IP) components for system-on-programmable-chip designers
This article was originally published on Electronicstalk on 18 Mar 2005 at 8.00am (UK)
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DFT cores provide a perfect fit
RF Engines has recently signed a contract with one of the leading mobile communications companies to supply high speed signal processing cores.
PFT core processes video 20 times faster than DSP
RF Engines has created a new way of simultaneously processing digital signals across a wide spectrum in real time.
They allow specialised and demanding multichannel receivers to be designed in a much shorter time scale and with a much-reduced technical risk.
This range of mixed-radix channel banks, along with rate converter and numerically controlled oscillator cores, allows highly optimised channelised receivers to be developed on small and cost-effective FPGA devices.
They are ideal for applications such as wireless communications nodes, medical instrumentation, radar, sonar, electronic surveillance, test instrumentation, real-time spectral analysis and satellite communications receivers.
Further reading
Speedy complex FFT core fits on million-gate FPGA
RF Engines (RFEL) has released details of its first product in its vectis family of multi-radix-architecture pipelined complex FFT cores.
Filter is reconfigurable RF spectrum channeliser
RF Engines (RFEL) has developed a radical new patented filter bank design, called the Tuneable Pipelined Frequency Transform (TPFT).
The Matrix range of cores is built around a set of different prime length DFT (discrete Fourier transform) cores.
When these different cores are combined, they allow "non-power-of-two" FFTs to be configured that exactly match the number of points required for the application.
When coupled with the rate convertor core, they allow a channel bank to be configured that exactly matches the required output spacing and sample rate.
As an example, in a recent design that required 1872 channels to be precisely extracted from a spectrum bandwidth in excess of 40MHz, 2-, 3- and 13-point DFT cores were integrated to produce this exact length FFT.
A simple 2048-point FFT would not have been able to meet the channel spacing and sample rate requirements for this application.
The design fitted comfortably within a Xilinx Virtex Pro50 FPGA with room to spare.
The design also included a complex rate convertor, Doppler correction and channel mapping capability.
John Summers, VP of Sales and Business Development at RFEL, said: "The release of these cores further demonstrates RFEL's commitment to providing our customers with the most optimised building blocks available for high performance digital signal processing".
"Also, our experience in complete receiver design enables us to understand the real needs of the system designer, and so we can simplify and 'de-risk' the product development programme".
These fully pipelined cores are available for licence in netlist form as a component ready to be combined with a customer's own IP.
Alternatively RF Engines can provide the core in bit-stream format for a complete chip design.
The Matrix cores can be used on both Xilinx and Altera FPGA families and can achieve continuous real time processing of complex data at up to 200Msample/s with faster speeds being possible by combining multiple cores.
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