Product category:
Intellectual Property Cores
News Release from: RF Engines | Subject: Matrix
Edited by the Electronicstalk Editorial
Team on 18 March 2005
DFT cores provide a perfect fit
RF Engines has recently signed a contract with one of the leading mobile communications companies to supply high speed signal processing cores.
RF Engines has recently signed a contract with one of the leading mobile communications companies to supply high speed signal processing cores The company in question, which prefers not to be named at this point, is incorporating the cores in its research and development programme
This article was originally published on Electronicstalk on 23 Jun 2004 at 8.00am (UK)
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RF Engines (RFEL) has released details of its first product in its vectis family of multi-radix-architecture pipelined complex FFT cores.
The RFEL designs are based on the high specification Matrix range of mixed radix discrete Fourier transform (DFT) cores, which are being integrated to produce a non-power-of-two filter bank.
Precise details of the design cannot be released at this time.
John Summers, RFEL's VP Sales and Business Development, stated: "We are obviously pleased to be supplying such a prestigious client with specialist designs, in support of its advanced technology programme, and we look forward to continuing to develop the relationship".
The Matrix family of core designs are built around a set of different prime length DFT cores.
When these different cores are combined, they allow "non-power-of-two" FFTs to be configured that exactly match the number of points required for the application.
This offers greater flexibility over the standard FFT algorithm, which is limited to power-of-two lengths.
As an example, in a recent design that required 1872 channels to be precisely extracted from a spectrum bandwidth in excess of 40MHz, 2-point, 3-point and 13-point DFT cores were integrated to produce this exact length FFT.
A simple 2048 point FFT would not have been able to meet the channel spacing and sample rate requirements for this application.
The design fitted comfortably within a Xilinx Virtex Pro50 FPGA with room to spare.
The building blocks are supplied as intellectual property (IP) components for system-on-programmable-chip designers, and are fully supported by bit-true simulation models.
They are ideal for applications such as wireless communications nodes, medical instrumentation, radar, sonar, electronic surveillance, test instrumentation, real-time spectral analysis and satellite communications receivers.
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