Compact cores create flexible resampling filters

A new range of fractional resampling architectures for FPGAs can be used to perform up-sampling or down-sampling of high-speed digital signals.

RF Engines has developed a new range of fractional resampling architectures for FPGAs that can be used to perform up-sampling or down-sampling of high-speed digital signals.

The designs are based on a novel architecture that offers significantly greater user flexibility in the design of the resampling filter and better dynamic range, when compared with designs based on traditional architectures.

The design is also unrivalled in its ability to efficiently handle thousands of channels simultaneously and independently.

Fractional resampling is a signal processing function that enables the manipulation of the signal sample rate, so that it may be precisely matched to the requirements of subsequent processing.

This has many applications, but RF Engines' designs are particularly relevant for matching symbol and sample rates in digital receivers, enabling the modulators and demodulators to be significantly simpler and cheaper.

Examples include telecommunications modulators and demodulators, image and video processing, audio processing, and interfacing to hardware components with fixed sample rates.

John Summers, RF Engines' VP of Sales and Marketing commented: "These fractional resampler cores are the latest addition to our range of high performance signal processing building blocks".

"The new cores achieve industry leading performance and flexibility".

"They provide designers with much greater freedom in their system design and the ability to do all this with low risk and to a shortened timescale".

"In addition, and perhaps most importantly, they can help to achieve significantly reduced overall system design costs".

The RF Engines architecture is highly scalable, and has a unique benefit in that it can support resampling of just one channel or thousands of channels simultaneously, while maintaining efficient use of silicon resources, and providing excellent filtering performance in order to mitigate the effects of aliasing.

The resampling rates can be selected with high precision, and allow selection of output sample rates with a resolution less than 1Hz.

When operating on multiple input channels, the architectures treat each channel independently, allowing different input sampling rates, and rate changes for each channel.

Furthermore, the rate change required for each channel can be updated at runtime, without affecting the operation of other channels.

The IP designs are provided as an EDIF netlist for either Xilinx or Altera FPGA devices, and are custom generated for each specific requirement to ensure a minimal FPGA footprint, and the lowest power consumption.

As with all RF Engines cores, the fractional resamplers are supported by bit-true Matlab models, allowing early validation of the core through simulation, and thereby reducing risk.

An example core for the Xilinx Virtex II Pro 50 FPGA is able to down-sample 512 channels simultaneously and independently.

The core supports maximum input channel sample rates up to 25Msample/s and a maximum aggregate sample rate for all channels combined of up to 280Msample/s.

Each channel can be down sampled by a user-selectable factor of up to one hundred with a sub-1Hz frequency resolution.

This particular core requires approximately 10% of the resources on the Pro 50.

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