Product category:
Intellectual Property Cores
News Release from: RF Engines | Subject: ChannelCore64
Edited by the Electronicstalk Editorial
Team on 27 October 2005
Digital down-convertor core runs on
FPGAs
RF Engines has introduced the first, fully flexible 64-channel digital down-conversion (DDC) core for use on FPGAs.
RF Engines has introduced the first, fully flexible 64-channel digital down-conversion (DDC) core for use on FPGAs ChannelCore64 has also been announced as a winner of the prestigious GSPx New Product Forum Award, making it the third year in a row that RF Engines has won such an award
This article was originally published on Electronicstalk on 21 Sep 2001 at 8.00am (UK)
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RF Engines (RFEL) has released details of its first product in its vectis family of multi-radix-architecture pipelined complex FFT cores.
ChannelCore64 allows designers to replace up to 16 specialist DDC ASIC devices with a single IP core for FPGA, significantly reducing board area, lowering power consumption, and increasing flexibility.
The new approach represents a major cost saving over traditional methods, with savings becoming more significant as the number of channels increases.
ChannelCore64 is targeted at applications such as wireless basestations, satellite ground stations, and other multi-channel radio receivers.
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Almost all radio receivers need to extract one or more relatively narrow channels from a much wider input spectrum in a process called down-conversion.
The trend towards increased flexibility within this part of the system is enabling interoperability between different radio access technologies, permits dynamic reconfiguration of band-plans, and future-proofs investment in receiver systems.
Furthermore, ever increasing user demand for bandwidth coupled with new technologies such as MIMO, means that systems must be capable of supporting an increasing number of channels.
ChannelCore64 uses a unique approach to down-conversion that achieves massively greater silicon efficiency per channel than other FPGA-based DDC solutions, while providing all the configuration controls that are typically associated with ASIC based DDCs.
The core fits comfortably within a Xilinx Virtex II Pro 30 FPGA device.
Furthermore, the end-to-end dynamic range offered by the core is significantly better than other available solutions, and a fractional re-sampler is included to allow output sample rates to be precisely configured.
The key features of ChannelCore64 are: support for two 16bit ADC inputs each with a sample rate up to 140Msample/s; 64 independent down-conversion channels, which may be connected to either ADC; independent tuning of channel centre frequencies with a resolution of better than 0.01Hz; independent selection channel bandwidths; independent selection output sample rates with a resolution better than 0.01Hz; and channel reconfiguration when core is running without affecting the operation of other channels.
A bit-true Matlab model is available free of charge which allows designers to accurately simulate ChannelCore64 within their system context.
The core is supplied under a simple licensing model, and custom variants, including up-convertors, can be produced on request.
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