IP core cuts signal processing down to size

Core provides subset of Cordic algorithm and uses a proprietary technique to more efficiently exploit the appropriate FPGA resources.

A new Vector Rotation/Translation IP core from signal processing specialist RF Engines offers a subset of the features provided by the traditional Cordic algorithm and, depending on the application, can deliver significant savings in cost, power and size.

Cordic stands for co-ordinate rotation digital computer, and is an algorithm (or set of algorithms) that is frequently used in practical signal processing applications for calculating a wide range of mathematical functions including logarithmic, hyperbolic and trigonometric functions.

The Cordic is commonly used, for example, in signal processing for radar systems, electronic warfare systems, and in linearisers for power amplifier designs.

The Cordic algorithm has long been recognised and used in electronic systems design, but the continuing trend towards intensive signal processing on FPGA has revealed limitations in how to efficiently implement the design on FPGA devices and, more specifically, the ability to trade-off specific FPGA resources for its optimal implementation.

Typically, the Cordic implementations that are generally available from mainstream FPGA vendors are heavily biased towards the use of the FPGA's logic resources, compared with the use of the DSP and memory block resources.

This heavy usage of the logic resources can often mean that, with a complex digital receiver front-end design, there are simply insufficient logic resources available in the FPGA to comfortably accommodate the logic-based Cordic and still achieve the required FPGA clock rate.

The new RF Engines Vector Rotation/Translation Cordic design addresses this issue and allows implementations which otherwise would be impracticable.

The key innovation is in the design of the vector rotation for the polar-to-rectangular co-ordinate transformation and vice versa, and the new approach uses a proprietary technique to more efficiently exploit the appropriate FPGA resources.

The new approach has been successfully demonstrated in recent customer digital receiver designs, and the Cordic has enabled the designs to be comfortably realised in a single FPGA, obviating the need for a second FPGA, and with the commensurate overall savings in system cost, sise and power.

A parameterised Matlab model (pcode) is also available for the new IP core, which can be used on any FPGA device that supports both multipliers and block memory.

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