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News Release from: Rambus | Subject: Rambus DDR3 memory controller interface cell
Edited by the Electronicstalk Editorial
Team on 18 October 2007
DRAM interface handles high data rates
The Rambus DDR3 memory controller interface cell is designed to accommodate applications including PC main memory, consumer electronics, servers, workstations and network communications.
Rambus has released a memory controller interface solution for industry-standard DDR3 DRAM The fully integrated hard macro cell provides the physical layer (PHY) interface between the controller logic and DDR3 or DDR2 DRAM devices for data rates of up to 1600 MHz
This article was originally published on Electronicstalk on 17 Nov 2003 at 8.00am (UK)
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Optimised for low power and reduced silicon area, the Rambus DDR3 memory controller interface cell is designed to accommodate a broad range of applications including PC main memory, consumer electronics, servers, workstations and network communications.
To serve these applications, Rambus has developed a DDR3 memory controller interface macro-cell that engineers can seamlessly integrate into their customer-owned tooling (COT) or application-specific integrated circuit (ASIC) chip.
"As signaling frequencies of mainstream DDR DRAMs continue to increase, the memory interfaces critical to system performance have become very challenging to design", said Martin Scott, Senior Vice President of engineering at Rambus.
"Using our extensive signal integrity experience, we have architected a low-risk, highly optimised DDR3 memory controller interface that meets the performance requirements of both main memory and consumer applications".
To ensure first-silicon success, a reliable system environment for high-volume production and rapid in-system qualification, the Rambus DDR3 interface solution incorporates a FlexPhase timing adjustment circuits for precise on-chip data alignment with the clock.
It also offers calibrated output drivers, on-die termination and a LabStation software environment for bring-up, characterisation and validation of the DDR3 interface in the end-user application.
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