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Networking Hardware
News Release from: SBS Technologies | Subject: FPGA-based SBCs
Edited by the Electronicstalk Editorial
Team on 24 December 2003
Tools speed high bandwidth development
FPGA technology has come a long way, says Ron Strauss, Vice President and General Manager, SBS Technologies.
Today, field programmable gate array (FPGA) technology has evolved to the point that FPGA chips can do much more than serve as a front end to I/O devices FPGAs can now handle the bulk of the processing in high-bandwidth and compute-intensive applications
This article was originally published on Electronicstalk on 19 Aug 2002 at 8.00am (UK)
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These recent advances allow embedded developers to deliver FPGA-based systems with an order of magnitude better price/performance ratio over existing multi-CPU or DSP systems.
Because of these cost/performance benefits, FPGAs are now being used for applications that are algorithm-intensive and require high bandwidth, such as medical imaging, numerous industrial applications, and sonar and radar for the military.
FPGA computing is an emerging technology, and much like the early days of embedded CPUs and DSPs, software tools are quickly maturing to simplify the development cycle for FPGA-based imaging applications.
As a result of these ease-of-use tools, FPGA computing is becoming an accepted alternative for high bandwidth and CPU intensive applications.
With the right development tools and software infrastructure to isolate the hardware layer of a conventional FPGA development environment, software programmers can leverage the advantages of new FPGA systems.
Today's tools ease development from infrastructure software that already "understands" the hardware to block level and C language software tools that enable quick links among user algorithms, internal soft-buses within the FPGA, and the resources of target hardware.
With the latest tools developers can accelerate the time-to-market for FPGA-based imaging applications in commercial, industrial, and military applications.
Not long ago, the human eye and brain were considered the best available technology for "second inspection" of semiconductors.
Second inspection takes place after a wafer is complete and has been electrically tested, a process that may leave behind marks.
Operators used to sit at microscopes scanning wafers for anomalies, sorting out what was acceptable from what was not acceptable.
Semiconductor wafer inspection is now a completely automated process, with a camera capturing a wafer's image and a processor often helping to resolve anomalies via a sophisticated image-processing algorithm that distinguishes between random markings and faulty wafers.
Today, automated optical inspection (AOI) processes speed manufacturing and eliminate errors on printed circuit boards (PCBs), glass panels, paper, film, foils, metallic lead frames, inkjet printer cartridges, and even plastic credit cards among other products.
Depending on the inspection system throughput required, some AOI systems perform image processing in software on a general-purpose CPU, whereas others use specific machine vision-processing hardware.
Multiple cameras often work in parallel, inspecting materials at high speeds, with anomalies resolved through multiple inspection algorithms that catch every flaw and virtually never make a false call.
Today imaging processing systems are also used to solve identification problems, such as in forensic medicine, for creating weather maps from satellite pictures, and for just about any application that processes images captured via digital camera.
Using a software algorithm running on a PC to process images captured by a camera is certainly much faster than old-fashioned methods.
Inspections have become faster because the software algorithms have improved.
But with these improvements comes more complex algorithms, which in turn slow down computing processes.
To that end, developers "burned in" or "hard-wired" these more complex algorithms on application specific integrated circuits (ASICs).
Custom designed for a specific application rather than a general-purpose chip such as a microprocessor, the use of ASICs increased performance over general-purpose CPUs because ASICs are "hard-wired" to do a specific job and do not incur the overhead of fetching and interpreting stored instructions.
The use of ASICs, however, is slowly declining because programmable logic devices such as FPGAs make it much easier to turn circuit designs developed in software into working chips.
That's because FPGAs do not require the creation of custom and expensive masking layers of ASIC manufacturing.
FPGAs, as mentioned earlier, have also greatly improved in speed, providing the necessary performance for high-bandwidth applications such as image processing.
Higher-speed processing can also be achieved by using more than one FPGA in parallel, with many processing paths helping to meet performance objectives.
In addition, as FPGAs are reprogrammable, they are much more flexible than ASICs and allow development to become an iterative process (much like software development) with code, compile, and test cycles.
This has made hardware design of FPGAs more of a do-it-yourself process, unlike ASICs, which must be completed before they can be used/and or tested.
As a result, initial cost of development is one primary reason FPGAs are more often used than ASICs.
Consider the difference in revenue and profit between systems developed using an FPGA versus an ASIC.
The development expenses are much higher using ASICs than FPGAs.
A developer can create a single chip FPGA-based system and change it later to suit the requirements of a given project.
With an ASIC, once a system has been developed, there's no turning back.
If you're not happy with the outcome or you want to update it with new features, you can't - you have to start from scratch.
FPGAs provide the design engineer the best of both worlds - the flexibility of software programmability with the speed of custom designed hardware.
FPGAs have not always been a panacea.
Before recent advances, there was a significant barrier to adoption of FPGA technology because they were difficult to program.
This is becoming less of a problem as vendors offer tools and vertical solutions that reduce the time of programming FPGAs.
In the past, FPGAs had to be programmed using a hardware definition language (HDL), a language used to describe the functions of an electronic circuit.
HDLs can be extremely complex, and there has been a shortage of engineers on the market who know how to use them to design hardware.
Fortunately, new tools enable engineers to program FPGA hardware using C/C++, with compilers that generate gate-level code that can be downloaded from a CPU to an FPGA.
Since C and C++ have become the language of choice for developing commercial software, many qualified C programmers on the market can apply their skills to designing FPGAs.
The real advantage is that algorithms previously too complex to program in HDL and too slow to run on a CPU can now be easily implemented in hardware.
Now system designers can marry a CPU or other types of chips such as a digital signal processor (DSP) to an FPGA to form a complex system with each IC doing what it does best.
Designers can now implement a system using a software compilation approach, with software portions of the design compiled to object code and hardware portions compiled directly to FPGA hardware.
Often design engineers will use an iterative software compilation approach to quickly find the best way of implementing a specific algorithm and then use HDL programming to create efficient, space saving code.
This enables designers to rapidly develop hardware for prototyping or production.
That is not to say that HDL programming will be eliminated altogether.
It can be up to three times faster to code in C, so many managers question if hard coding is worth the effort.
However, there are some parts of almost any program that can run more efficiently if coded directly to hardware, and fortunately, tools are now available that allow developers to code in HDL much faster.
For example, chip vendors are offering programs that enable designers to develop high-performance system-on-a-programmable chip designs that accelerate the time to market by automating the system definition and integration phases of SoPC development.
Designers can compose bus-based systems out of common system components, from very simple blocks of fixed logic to complex subsystems, using an intuitive wizard-based graphical user interface (GUI).
Some building blocks included in the SoPC builder library include processors, intellectual property (IP) - which refers to the algorithms used within hardware circuits and software - peripherals, memory interfaces, communications, buses and interfaces, digital signal processing (DSP) IP, generic C drivers, operating system kernels, and more.
System-level design tools are now available that assist with algorithm development, simulation, and verification.
This accelerates time to market by automating the system definition and integration phases of SoPC development.
These tools now enable a designer to easily implement the hardware of a system comprised of embedded CPUs, FPGAs, and DSPs rapidly.
Knowing that many designers are going to create systems with multiple embedded CPUs and FPGAs, some vendors offer boards that include both, complete with buses and serial connections to allow them to communicate.
These types of solutions are best used for high bandwidth applications that also contain complicated algorithms for applications such as image processing.
The board usually comes with an integrated development environment (IDE) that provides APIs, drivers, memory controllers, sample applications and source code.
Ideally IDE is integrated with FPGA development tools and a bus architecture for easy system development using block-level software libraries for fast time-to-market.
Such a board should deliver a high-bandwidth pipeline across many FPGA processors coupled with high-speed memory.
To take full advantage of the real time processing FPGAs offer the primary data path from I/O devices to the first FPGA should be greater than 1Gbyte/s or, better yet, more than 3Gbyte/s.
A mezzanine I/O data connector on the board can be used to enable the attachment of a CameraLink, video, or any other digital or analogue device.
To that end, packages are also available that include an FPGA/CPU board and related software and development tools, plus a CameraLink mezzanine I/O board, and all the required software to get an image-processing solution off the ground, including trigger and encoder control hardware and software, camera emulator diagnostic tools, a tutorial, documentation and example applications, pixel re-order and tap configuration tools, and more.
An FPGA-based image processing application is only one example of how vendors can make it much easier for developers by anticipating their need for application-specific interfaces and software modules.
Vendors can provide the basic infrastructure, FPGA development tools, and vertical solutions such as mezzanine boards for a camera or video application.
Developers can then add specific logic elements to the solutions to quickly complete their project and take advantage of the superb price/performance of FPGA computing.
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