Sundance enters partnership with Dillon

Sundance has entered a partnership with Dillon Engineering to deliver a product that provides leadership in the fixed width and floating point FFT FPGA market.

The product offers Dillon's benchmark portfolio of Fast Fourier Transform (FFT) IP on the Sundance SMT702 dual ADC, PXIe embedded computing module.

The combination of Dillon's cores and Sundance leadership in modular FPGA design gives developers access to a configurable embedded product.

Dillon's FFT cores are area efficient and occupy fewer FPGA logic resources in terms of XtremeDSP slices and Brams than comparable off-the-shelf FFT cores.

Dillon's IEEE-754 Floating-point FFT core sustains a rate up to 250Msps.

It offers up to 64M points.

The joint product is supported by design support from the 3L Diamond multiprocessor tool suite and a bit-accurate and Matlab compatible C/C++ model, testbench, datasets and data generators.

Dillon's FFT cores are initially available on the Sundance SMT702 module.

They are pipelined for continuous processing.

They include: parallel and dual parallel for concurrent processing and extreme performance of more than 25Gsps; ultralong using the SMT702s external DDR2 Sdram for long transforms up to 64M points; parallel butterfly; mixed radix; and 2D/3D multi-dimensional FFT processing.

The SMT702 is fitted with the Xilinx Virtex-5 LX110T-3 FPGA and delivers data rates of up to 250Msps and up to 64M points IEEE-754 single precision FFT.

The FPGA is optimised for high-performance logic with low-power serial connectivity.

It is supported by two banks of 64-bit 512Mb DDR2 Sdram and dual 3GHz ADC that can be combined to deliver 6Gsps.

Eight-lanes of PXI Express deliver 16Gb/s of effective bandwidth per direction.

The module can plug in to any PXI Express peripheral slot or any PXI Express hybrid slot.

Dillon Engineering's pipelined floating-point FFT uses modular Radix-2 FFT architecture to provide discrete transform on data frames or continuous data streams, with sample rates up to the maximum clock frequency.

This efficient structure employs a single butterfly and single delay feedback path per rank for low localised memory usage.

True IEEE-754 floating-point data is maintained throughout, supporting a dynamic range of data without requiring complicated fixed-point analysis.

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