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News Release from: Silica | Subject: IBM PowerPC 405
Edited by the Electronicstalk Editorial
Team on 29 June 2006
FPGA core runs 32bit PowerPC
The IBM PowerPC 405 is a hard 32bit RISC CPU core immersed directly into the Xilinx FPGA fabric to implement high performance embedded applications.
The IBM PowerPC 405 is a hard 32bit RISC CPU core immersed directly into the Xilinx FPGA fabric to implement high performance embedded applications The PowerPC 405 processor is a 32bit implementation of the PowerPC embedded environment architecture that is derived from the PowerPC architecture
This article was originally published on Electronicstalk on 29 Jun 2006 at 8.00am (UK)
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Specifically, the PowerPC 405 processor is an embedded PowerPC 405D5 (for Virtex-II Pro) or 405F6 (for Virtex-4) processor core.
The combination of dual hard PowerPC core systems integrated with co-processing capability enables a wide range of performance optimisation options, and integrates a scalar five-stage pipeline, separate instruction and data caches, a JTAG port, trace FIFO, multiple timers and a memory management unit (MMU).
The advanced process technology enables the embedded PowerPC 405 core to operate at up to 450MHz and deliver over 700DMIPS in the Virtex-4 FX device.
The Virtex-4 devices implement an auxiliary processor unit controller (APU), which provides embedded system designers with the flexibility to extend the native PowerPC 405 instruction set and significantly improve software algorithm execution utilising application-specific hardware accelerators implemented in the FPGA logic.
Designers can create user-defined instructions for hardware acceleration to achieve a more efficient integration between an application-specific function and the PowerPC processor.
Using the high bandwidth, low latency interface established between the APU controller and the FPGA fabric, the APU controller decodes high-performance load and store instructions between the processor data cache or system memory and the FPGA fabric.
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