An alternative approach to bit error rate testing

Steven Robalino discusses a test methodology that may be applied to a wide range of datacommunications systems and devices which transmit data over a serial bus.

The traditional method of design margin testing in serial datacommunications systems is to employ a specially designed bit error rate (BER) tester.

Although BER testers have proven effective, they are typically expensive and they do not always exercise the system under test with the same level of noise or using the same data patterns that will be seen by the system in the field.

This can leave some design flaws undetected.

To ensure that all design flaws are found prior to product release, it is best to test the system while it is under a real world load - including eye-pattern variances and worst case data patterns.

This article discusses a test methodology that may be applied to a wide range of datacommunications systems and devices which transmit data over a serial bus.

This test methodology may be part of the design verification process or it may be used to qualify substitute components after the product has been released to production.

The example below describes how the methodology was used to debug a Fibre Channel switch.

The test setup incorporates a Fibre Channel host bus adapter (HBA), a PC housing the HBA and running test software, and two signal generators.

The test methodology was used to uncover a latent design flaw that had not been detected using a BER tester.

A Fibre Channel switch was tested for data reliability as part of the design verification process.

The test setup included two signal generators, PC with a Fibre Channel HBA installed and the system under test (a Fibre Channel switch with 2Gbit/s datarate).

The digital output of signal generator A is connected to clock input of the Fibre Channel HBA, the differential output of signal generator B is connected to the clock input of the switch.

The HBA is connected to the Switch via a standard Fibre Channel link.

The PC hosting the Fibre Channel HBA is also running test software which simulates real-world data access.

The signal generators incorporate highly programmable sweep capabilities that are able to drive multiple clock types and input levels.

Signal Forge signal generators were chosen because they the sweep capability as well as provide a digital output with programmable voltage level, as needed to drive the Fibre Channel HBA, and the differential output needed by the system under test (SUT).

The frequency of the HBA and the SUT were programmed into the respective signal generators and the frequency sweep range was set for the worst-case range for each device as specified by the Fibre Channel standard.

The rate of change of the frequency was set to a unique value for each signal generator in order to prevent the HBA and SUT from switching in unison.

The following equation was used to determine the deviation range: ppm x F(MHz) = deviation (Hz).

The HBA required a 53MHz, 1.8V digital clock source and the switch required a 212.5MHz differential clock source.

The digital output of signal generator A was connected directly to the HBA using a short length of coax wire.

Signal generator B was connected to the Fibre Channel switch through a voltage convertor.

The voltage convertor is needed since switch requires a CML voltage level and the signal generator output is LVPECL.

The conversion was accomplished by AC-coupling the SUT's input to the signal generator's differential output and adjusting the Vtt voltage level to achieve the proper voltage parameters.

(A schematic for the voltage convertor may be found in the version of this article located on the Signal Forge website).

First, the integrity of each component of the system under test was verified individually.

This was done by sweeping the clock of each component from min to max.

After successfully completing the component test, a test of the interconnected system was conducted by sweeping the reference clock input of both the HBA and the SUT simultaneously.

It was important to keep the inputs to the serdes PLL reference clock of the HBA and the SUT from changing in unison because if the two clocks were allowed to change at the same rate, margin testing would not occur.

To keep the signal generators from changing in unison, the output of signal generator A and signal generator B were programmed for different deviation, step size and step rate.

With the two clocks changing at different rates they are never in phase allowing all corner cases to be found.

This setup allowed the interconnected system to be tested in a real world environment and verified that the entire system maintained the required setup and hold under all conditions.

Next, the signal generators were set to displace the centre frequency by +/-200ppm as specified by the Fibre Channel standard.

While the HBA and SUT clock inputs were being swept, test software was reading and writing data through the interconnected system.

The test software was written in Visual Basic using standard operating system handles for I/O operations.

The software was programmed to send, retrieve and compare data of variable size files, in a worst case data pattern, from the PC, through the HBA, to the switch and back.

After running the test for 12 hours, a data transmission error was detected indicating a data pattern sensitivity in the SUT - a bug not detected by the BER tester - which would require a silicon spin of the switch ASIC to correct.

In order to reduce the impact to the product delivery schedule, it was critical that the time to reproduce the bug be reduced significantly.

To do this, ten of the test beds described above were set up and run simultaneously.

This enabled the design team to reproduce the error in a just a few minutes.

This methodology saved two months of development time and found a critical bug during the development cycle rather than after product release.

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