Product category:
Design and Development Hardware
News Release from: Silicon Concepts | Subject: ispPAC 30 system design kit
Edited by the Electronicstalk Editorial
Team on 06 May 2002
Easy introduction to programmable
analogue devices
The ispPAC 30 system design kit allows fast and easy development of analogue designs using Lattice ispPAC programmable analogue components, including the new ispPAC 30 device.
The ispPAC 30 system design kit, available from Silicon Concepts, allows fast and easy development of analogue designs using Lattice ispPAC programmable analogue components, including the new ispPAC 30 device The kit includes PAC-Designer system software, ispDownload cable, ispPAC 30 evaluation board, and a Lattice ispPAC 30 device sample
This article was originally published on Electronicstalk on 10 Apr 2002 at 8.00am (UK)
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Evaluation boards for other ispPAC family members are available separately or in additional design kits.
Analogue circuit designs are configured graphically using the intuitive Microsoft Windows compatible Lattice PAC-Designer software.
Design parameters can be entered or edited by using the mouse to 'point and click', including interconnections, gain, pole frequency, programmable references, multiplying DACs, comparators and other circuit characteristics.
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Fast design simulation, including gain/phase plots, is easily accomplished within the same environment.
When the design is complete, the analogue device can be programmed and reprogrammed in system via the download cable, connected to the host PC parallel port.
Device programming is supported by an on-chip IEEE 1149.1 JTAG/SPI interface.
Documentation is also provided, and the kit is supported by a 12 month maintenance agreement.
The Lattice ispPAC device family are dynamically reconfigurable analogue devices, fabricated on E2CMOS technology for nonvolatile configuration storage.
The ispPAC30 is the latest device to join the family and also features SRAM registers for unlimited reconfigurability.
Featuring four programmable gain instrumentation amplifiers, two multiplying DACs and two configurable output amplifiers with 'rail to rail' outputs, it is integrated into a single 24-pin SOIC package or 28-pin DIP.
The device allows designers to quickly configure and fine-tune data acquisition systems, voltage monitoring circuits, laser diode controllers and many other analogue circuits such as programmable analogue signal control loops and precision programmable gain amplifiers.
Lattice's in-system programmable (ISP) technology supports reconfiguration of ispPAC devices in the field, allowing on-the-fly adjustments, functional reassignment of the device, and remote updating of equipment.
IspPAC devices operate from a single 5V supply, and also feature standby modes to reduce current consumption to just a few microamps.
The ispPAC architecture features an analogue routing pool that interconnects programmable analogue cells (PACells), allowing on the fly reconfiguration and the elimination of the parasitic effects associated with printed circuit routing.
The input PACells and output PACells of ispPAC devices display low offset voltage, low gain error and rail to rail output swing, and allow analogue designers to precisely determine programmable gain, continuous time filter characteristics, analogue signal arithmetic, programmable integration time constant and many other circuit parameters.
Further integrated features common to ispPAC family members include programmable precision voltage references, 2.5V reference output, JTAG/SPI interface logic and configuration memory and autocalibration.
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