Frugal CPLDs draw next to no power

Edited by the Electronicstalk editorial team Feb 19, 2003

New CPLDs from Silicon Concepts draw almost no power at all, consuming 80% less than alternatives, yet still deliver a blistering 256MHz performance.

New CPLDs from Silicon Concepts draw almost no power at all, consuming 80% less than alternatives, yet still deliver a blistering 256MHz performance.

Based on Lattice's already popular ispMACH 4000 architecture, the ispMACH 4000Z family, available from Silicon Concepts, delivers both low dynamic and static power and high speed.

In operation at maximum frequency, ispMACH4000Z family devices consume less than 25mW typical and standby current is typically only 20uA from a 1.8V supply, compared with a more normal 100uA.

Lattice has managed to achieve high performance, with a 3.5ns pin-pin delay, allied to this very low power consumption by using a low leakage version of its advanced EECMOS process.

To open the device to the widest possible application areas, Lattice is offering the CPLD in automotive as well as industrial and commercial temperature range versions.

Powered from 1.8V, the 4000Z family supports a wide range of 3.3, 2.5 and 1.8V I/O standards and features 5V tolerant I/Os when using the LVCMOS 3.3 interface.

The new parts are pin and function compatible with existing CPLDs from the Lattice ispMACH 4000 families, also supported by Silicon Concepts.

The ispMACH 4000 family includes 3.3, 2.5 and 1.8V power supply versions, designated the ispMACH 4000V, ispMACH 4000B and ispMACH 4000C devices, respectively.

The ispMACH 4000 devices couple industry leading speed performance with the lowest dynamic power consumption available while supporting I/O standards between 3.3 and 1.8V.