Product category:
Intellectual Property Cores
News Release from: Silicon Hive | Subject: Bresca, Avispa OFDM and FEC Suite
Edited by the Electronicstalk Editorial
Team on 07 June 2005
DTV receiver SoC showcases IP cores
Silicon Hive has demonstrated a DTV receiver incorporating the world's first fully programmable system-on-chip (SoC) for digital TV demodulation.
Silicon Hive has demonstrated a DTV receiver incorporating the world's first fully programmable system-on-chip (SoC) for digital TV demodulation Silicon Hive IP cores enabled the SoC to be produced in less than one year
This article was originally published on Electronicstalk on 18 Jun 2003 at 8.00am (UK)
Related stories
Reconfigurable processors target soft radios
A comprehensive new hardware/software codesign solution allows SoC designers to leverage the performance advantage of reconfigurable computing.
Cores boost video signal processing
HiveFlex VSP2100 Series of processor cores targets HD widescreen TVs with high quality video displays.
Full programmability introduces a new era for SoC developers.
The IP cores simultaneously address time to market, multi-standard, and performance risk issues, common in consumer electronics and mobile communication markets.
Silicon Hive built the entire programmable demodulator SoC using three of its IP cores, which are available for licensing: Bresca baseband (a programmable IF front-end), Avispa OFDM (a programmable frequency-domain processor), and Silicon Hive's FEC Suite (a programmable error-correction subsystem).
The SoC entertains a robust software development environment used to create new demodulator designs, which can be validated in field trials before committing them to silicon with cost-down optimisations.
Silicon Hive now offers a third-generation processor built on this experience: the Avispa-CH1 communications processor recently announced at InStat's Spring Processor Forum.
Avispa-CH1 supersedes Avispa OFDM, delivering higher performance at a smaller silicon footprint.
It achieves two sustained complex multiply-accumulates per cycle, two sustained FFT butterflies per cycle, and four sustained semicomplex FIR taps per cycle.
The architecture is fully scaleable, enabling increased performance.
The new Avispa-CH1 is available for licensing immediately.
All the cores are offered with programming tools, application libraries, and reference designs for common DTV terrestrial, cable, and satellite standards, such as: DVB-T, DVB-H, ISDB-T, DVB-C, DVB-S and T-DMB.
Using this basis, SoC vendors can quickly develop their own cost effective demodulator solutions with differentiation in performance, as well as multi-standard functionality for DTV mobile terminals and fixed appliances.
Applicable devices include mobile phones, digital television, personal computers, DVD recorders/players and set top boxes.
• Silicon Hive: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page

