Product category:
Communications ICs (Wired)
News Release from: Silicon Laboratories | Subject: Si5318
Edited by the Electronicstalk Editorial
Team on 23 March 2005
Clock multiplier exceeds Sonet
specifications
The Si5318 is the latest addition to the family of precision clock multiplier ICs capable of generating the ultra-low-jitter reference clocks required in high-speed Sonet/SDH line cards.
The Si5318 is the latest addition to the Silicon Laboratories family of precision clock multiplier ICs capable of generating the ultra-low-jitter reference clocks required in high-speed Sonet/SDH line cards Based on the company's DSPLL technology, the Si5318 delivers jitter generation as low as 0.7ps RMS, far lower than OC-48/STM-16 jitter specifications, while requiring no external components and less than one-fifth the board space of discrete solutions
This article was originally published on Electronicstalk on 12 Feb 2004 at 8.00am (UK)
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Unlike competing solutions based on hybrid combinations of analogue circuitry, crystals or SAW-based oscillator elements, Silicon Laboratories' precision clock ICs are based on its patented DSPLL technology, which uses digital signal processing techniques to create a fully integrated phase-locked loop (PLL).
The wide tuning range of the DSPLL enables one design to support a broad range of frequencies that would traditionally require multiple crystal or SAW-based PLLs.
This frequency agility allows one Si5318 design to handle both Sonet/SDH and forward error correction (FEC) rates, minimising bill-of-material (BOM) complexity and saving R and D expense.
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"The Si5318 is the smallest, most highly integrated jitter attenuating PLL IC designed for the OC-48/STM-16 market", said Brad Fluke, Vice President and General Manager of Silicon Laboratories.
"Silicon Laboratories is committed to providing innovative timing solutions for the networking market and will continue to be a leader in performance and integration for precision clock applications".
Silicon Laboratories' DSPLL technology relies on a low phase noise, high frequency on-chip digitally-controlled oscillator (DCO) to produce a frequency agile, low jitter output clock with jitter performance rivaling that of discrete solutions.
The low phase noise characteristic of the silicon-based DCO enables narrowband loop operation for applications requiring jitter attenuation.
The Si5318 provides user-selectable loop filter bandwidths ranging from 800Hz to 12,800kHz, allowing the user to easily match the level of jitter attenuation to the amount of clock cleaning required by the application, a feature not available with discrete PLL solutions.
As the DSPLL integrates all PLL components into a single device, it provides greater immunity to system noise sources and simplifies layout.
Competing solutions built with discrete PLL components have multiple noise entry points, which require special layout precautions to protect sensitive analogue nodes from board level noise that can increase clock jitter.
The Si5318 generates a single output clock in the 19 or 155MHz range from a reference input ranging in frequency from 19 to 155MHz.
The Si5318 is packaged in a 9 x 9mm CBGA.
The Si5318 is priced at $32.00 in quantities of 1000.
Samples are available now with volume production available in July 2005.
An evaluation board, the Si5318-EVB, is also available for $350.
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