Product category:
Design and Development Software
News Release from: Solido Design Automation | Subject: SolidoStat
Edited by the Electronicstalk Editorial
Team on 17 September 2007
Software cuts parametric yield loss
SolidoStat is a Stat tool for transistor-level statistical design and verification.
Solido Design Automation has released software for the semiconductor industry that solves the problem of preventable parametric yield loss in integrated circuit design SolidoStat is a Stat tool for transistor-level statistical design and verification
This article was originally published on Electronicstalk on 16 Jan 2006 at 8.00am (UK)
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According to Amit Gupta, Solido's cofounder and CEO, as semiconductor process technologies and supply voltages shrink, microscopic local and global statistical variations adversely impact chip designs.
"Lower yields translate into higher costs and lower production capacity, and subtract from the bottom line for the most sought-after consumer electronics".
"The semiconductor industry can't afford to operate with a handicap on supply".
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"Stat tools provide a solution to this design/manufacturing problem".
"Three goals of all design teams are to avoid yield loss and over-design, improve design robustness, and maximise designer productivity".
"When design teams achieve these goals, semiconductor companies and consumers win because it reduces their costs and gets products to market faster".
"Solido has produced an elegant solution to address these key areas for transistor-level nanometer designs".
SolidoStat provides an efficient way for chip designers to gain insight into the effects of process variations on their design, and also to make the design more robust to these effects without over-designing.
For example, after using SolidoStat for one day on a filter design, a design team identified that variations in insertion loss, attenuation, and bandwidth were causing yield loss.
SolidoStat pinpointed which devices and statistical variations were the source of the problem.
It then automatically revealed better design options and identified the tradeoffs in attenuation, bandwidth, gain flatness, insertion loss, power, and total harmonic distortion that would improve yield.
SolidoStat produced an acceptable path for improving yield to nearly 100%.
The SolidoStat suite includes five tools that add new capabilities to the IC design flow; SolidoStat Sampler, Characteriser, Circuit Enhancer, Tradeoff Analyser and Visualiser.
The SolidoStat Sampler accelerates traditional Monte Carlo analysis through parallel processing and high-efficiency sampling algorithms.
Graphical output and data analysis provide answers to key design questions such as, "What are the problematic specifications and statistical distributions?" and "Which environmental conditions will cause problems in the design?".
The SolidoStat Characteriser uses algorithms to pinpoint sources of yield and performance loss in the design, reducing the problem from thousands of parameters to just a handful of significant parameters.
This multivariate approach flags sensitive devices and zeroes in on transistor, resistor and capacitor geometries that could be changed to improve the design.
The SolidoStat Circuit Enhancer automatically and intelligently explores sizing alternatives to improve the circuit's robustness.
Designers can compare candidate solutions and choose the one most suitable for their application.
The SolidoStat Tradeoff Analyser mines sampler results, without additional simulations, to identify tradeoffs between specifications that improve yield.
The SolidoStat Visualiser converts raw data from all the analyses into dynamic visual representations that offer designers key insight into their circuits.
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