Product category:
Design and Development Software
News Release from: Sequence Design | Subject: CoolTime
Edited by the Electronicstalk Editorial
Team on 06 March 2003
Simultaneous analysis for electrical
integrity
Sequence Design has unveiled its CoolTime technology, the foundation of an industry-first "instantaneous" voltage-drop analysis tool.
Sequence Design has unveiled its CoolTime technology, the foundation of an industry-first "instantaneous" voltage-drop analysis tool that will join the company's burgeoning portfolio of electrical-integrity analysis solutions for nanometre SoC design Power, voltage drop, timing and signal integrity are interrelated and cannot be examined in isolation
This article was originally published on Electronicstalk on 3 Feb 2004 at 8.00am (UK)
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CoolTime analyses these electrical effects concurrently, and reduces runtimes over existing, fragmented solutions by up to 75%.
CoolTime is being demonstrated for the first time this week in the Sequence booth at Munich's DATE trade show.
The technology will be available commercially in Q2, 2003.
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"Companies at the leading-edge of design, noted experts such as the University of Michigan's Dr Dennis Sylvester, and even Dr Andy Grove, Chairman of Intel, are evangelising the importance of power integrity in the nanometre realm", said Vic Kulkarni, President and CEO of Sequence.
"Within our NanoCool initiative, CoolTime provides an advanced analysis platform with a focus on power and signal-integrity issues.
By addressing advanced physical effects, it ensures consistency of results and dramatically increases the probability of first-time silicon success for complex designs".
CoolTime overcomes inherent limitations in existing cell-based IR-drop tools.
Rather than a static approximation of time-variant currents, CoolTime performs instantaneous current analysis to incorporate dynamic effects resulting from power-grid capacitance, package inductance, and on-chip decoupling capacitors.
For designs under 130nm, these dynamic effects can contribute to as much as 30 to 50% of the total voltage drop.
CoolTime examines both power and ground networks simultaneously to account for ground-bounce and power grid resonance.
Benchmarks from beta customers provide convincing evidence of the tool's effectiveness.
CoolTime's instantaneous mode runs at a rate of 2 million gates per hour, while static results scale to 25 million gates per hour and beyond.
The embedded high-speed extractor is scalable and can process millions of net segments per hour.
"Instantaneous analysis is a requirement for accurately modeling inductive noise and decoupling capacitor effects", said Dr Anantha Chandrakasan, Professor of EECS at MIT.
"Furthermore, delay effects cannot be modelled effectively using voltages computed from time-averaged currents".
For the analysis of current, CoolTime has a patent-pending instantaneous vectorless algorithm, T2, that relies on timing constraints as user input.
Unlike existing statistical approaches, it does not rely on probabilistic activity propagation methods, instead computing actual events on circuit nodes.
In addition, the tool supports simulation-based voltage-drop analysis, and can compute average IR drop for fast analysis during the pre-route phase to identify hot spots, structural weaknesses in the power grid, and via deficiencies.
CoolTime features: Instantaneous voltage-drop analysis, including power grid capacitance, on-chip decoupling capacitors, and package inductance (2 million gates/hour); the T2 timing event based instantaneous currents algorithm for worst-case voltage drop analysis; fast average IR-drop analysis for power grid correction (25 million gates per hour); simultaneous analysis of power and ground networks; high-speed hierarchical power grid extraction; a graphical interface that includes easy-to-use wizard and voltage-current-recorder (VCR) and LEF/DEF interface along with support for external power grid SPEF; SDF output with crosstalk and voltage drop delays for signoff timing analysis flows; event-window based timing and signal integrity analysis for crosstalk and voltage-drop effects; detailed reporting on voltage drop, power, timing and signal integrity; SoC performance and capacity for up to 25 million gates; and physical optimisation for timing and signal integrity from the same platform.
While emphasising its strengths in instantaneous voltage drop analysis, CoolTime simultaneously leverages production-proven Sequence technologies for power, parasitic extraction, timing, and signal-integrity analysis.
In addition to crosstalk-induced delay and glitch, CoolTime accounts for voltage-drop induced delays during timing analysis.
CoolTime renders a complete timing and signal-integrity capability that accounts for on-chip and off-chip physical effects.
With a built-in characterisation engine for derating delays for voltage drop, CoolTime augments existing timing library formats for accurate timing analysis.
An SDF output with voltage drop and crosstalk induced delays can be generated from CoolTime for signoff timing analysis.
CoolTime augments and complements the user's installed physical implementation flow for fast, full-chip signoff of hierarchical SoC designs by eliminating the need for multiple analysis tools and multiple iterations.
CoolTime shares a common platform with Sequence's PhysicalStudio for pre- and post-route optimisation of timing and signal integrity, thereby enabling fast and accurate design closure for nanometre SoC designs.
The production release of CoolTime will be available in Q2, 2003.
The US base price for an annual licence is $150,000.
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