Product category:
Design and Development Software
News Release from: Sequence Design | Subject: PhysicalStudio
Edited by the Electronicstalk Editorial
Team on 21 May 2003
Signal-integrity tools speed graphics
chip design
Faced with the need to create a series of the world's most advanced graphics chipsets, and meet time to market deadlines, Nvidia Corp has revved up its design flow with Sequence's PhysicalStudio.
Faced with the need to create a series of the world's most advanced graphics chipsets, and meet time to market deadlines, Nvidia Corp revved up its design flow with Sequence's PhysicalStudio, successfully employed in six tapeouts so far After an extensive review, the Sequence tool was chosen for its ability to readily and accurately optimise signal integrity (SI) and timing in very large, complex chips
This article was originally published on Electronicstalk on 9 May 2003 at 8.00am (UK)
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Further reading
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Sequence Design is porting all its tools to Linux, and the first Linux-compatible products were featured in the company's DAC demo suite earlier this month.
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Sequence Design has unveiled its CoolTime technology, the foundation of an industry-first "instantaneous" voltage-drop analysis tool.
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When Telasic Communications started searching for an extraction tool, its design team had two major requirements.
We are pushing the design and performance metrics beyond previous limits by relying on world-class tools from companies like Sequence".
One of the most difficult tasks facing Greco's team was signal integrity and timing closure.
"PhysicalStudio provides a very accurate prediction of the timing impacts of coupling, and a convergent and minimal impact method of fixing these effects".
"If Nvidia, a leader in the worldwide fabless market, is concerned with signal integrity, then everyone should be", said Sequence President and CEO, Vic Kulkarni.
"SI is becoming an increasingly critical challenge as the performance frequency of designs goes up, transistor counts multiply, processes shrink and introduce their own nuances, and design cycles are compressed to satisfy time-to-market pressures.
We are honoured to be assisting Nvidia with addressing the challenges of nanometre design".
Recognised by Fortune Magazine as one of the chips that will "change your life", the Nvidia GeForce FX GPU is the industry's first GPU to deliver real-time, cinematic quality graphics and special effects on the desktop PC.
Featuring the Nvidia CineFx engine, and support for high-level programming languages such as Cg, the GeForce FX GPU delivers visual effects on par with the hottest motion pictures.
Packing nearly twice the number of transistors as previous Nvidia GPUs, the GeForce FX GPU also uses the industry's most advanced 130nm manufacturing process, enabling developers to create compelling content of unrivalled beauty, running at unmatched speeds.
There are four major SoC design-closure issues: timing, signal integrity, power, and clock.
All are interdependent, necessitating a concurrent view resolve them.
Resolving them calls for a blend of extraction, timing analysis, signal-integrity analysis, and optimisation in a single engine.
Failure to account for these effects concurrently, inevitably leads to diminished performance, and increased time to market.
PhysicalStudio optimises chip timing and signal integrity issues concurrently, both before and after routing.
It is fully interoperable with industry-standard routing tools, permitting existing physical design flows to reach fast, predictable design closure in silicon geometries below 180nm.
PhysicalStudio allows system-on-chip designers to: reach 35% higher clock speeds; achieve a 5-15% reduction in power over traditional physical design flows; compensate for signal integrity effects, such as crosstalk-induced "setup" violations and "hold" violations, and functional "glitch" errors; accurately predict and immunise against noise during placement; and surgically correct timing and signal-integrity issues "along the route" using a patent-pending FullContext post-route technique.
By unifying optimisation after placement and post-route optimisation into a single engine, the product ensures that every net in a design is correctly driven and all timing and signal integrity violations are eliminated.
PhysicalStudio operates on large, hierarchical designs with varying abstractions at the top-level such as register-bounded blocks, Stamp, LIB and CLF.
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