Product category:
Design and Development Software
News Release from: Sequence Design | Subject: PhysicalStudio
Edited by the Electronicstalk Editorial
Team on 27 May 2003
Optimisation package turns to leakage
current
Sequence Design has launched a joint development effort with Toshiba Corp to optimise power and reduce wasted power consumption in semiconductors.
Sequence Design has launched a joint development effort with Toshiba Corp to optimise power and reduce wasted power consumption in semiconductors This methodology is based on Toshiba's Selective MTCMOS (multi-threshold CMOS) technology
This article was originally published on Electronicstalk on 9 May 2003 at 8.00am (UK)
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The problem of leakage currents is growing at an exponential rate at line widths below 90 nanometres, according to Takashi Yoshimori, System LSI Division Technical Executive, Toshiba Semiconductor.
"It is now common for 20% or more of a chip's power budget to be consumed by leakage power alone, severely limiting the designer's ability to maximise circuit efficiency and performance", Yoshimori said.
"Sequence's leakage power methodology provides us with a way to turn the power supply to logic on and off as needed, eliminating waste and greatly extending battery life for handheld products".
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"We are honoured to have the opportunity to partner with Toshiba to address the industry's growing concern about low power design.
As Dr Gordon Moore noted at this year's ISSCC conference, leakage power is a trend that is spiralling out of control", said Vic Kulkarni, Sequence President and CEO.
"By working in concert with the most advanced design and process-science talent, we can be assured that our joint breakthrough on leakage power will be well suited to the challenge of power consumption at the nanometre level".
Leakage control has become a major design issue due to leakage currents that drain a battery's charge even when a wireless device is inactive or in standby mode.
Transistors in each new process generation are leakier than those in previous generations (due to transistor scaling effects), only exacerbating the problem.
Leakage is also an issue in active mode, when the transistors are operational, as any power wasted due to leakage is not available to be allocated to performance enhancing logic - that is, leakage power comes right off the top of the overall power budgets.
The Sequence power methodology includes fully automatic gate level power optimisation technology for the reduction of both dynamic and leakage power.
The optimisations may be run independently or together with no adverse impact on area or timing.
Sequence's power optimisation tools reduce both active and standby leakage currents.
Active mode leakage is reduced through the use of two optimisation features: Dual-threshold (dual-Vt) substitution and resizing.
Both features work by trading off positive slack timing for reduced leakage.
The Dual-Vt optimisation substitutes high-Vt cells (which are slower but leak much less) along fast paths.
Resizing optimisation reduces transistor size along fast paths and results in reduced leakage since smaller transistors leak less.
Resizing also reduces dynamic power.
Sequence, in partnership with Toshiba, is adding to its power optimisation suite by developing an MTCMOS optimisation tool.
MTCMOS, sometimes referred to as power-gating, works to reduce leakage currents by disconnecting the power supply from portions of the circuit when those portions are inactive.
Leaking currents are prevented by inserting a series switch transistor between the logic cells and the power supply or ground.
The switch is closed when the logic is operational and opened when the logic is inactive.
Reductions of 10x to 100x in leakage can be achieved.
Sequence's MTCMOS approach uses patent pending optimisation algorithms that result in minimum area overhead and no performance degradation.
All physical design issues are automatically resolved while concurrent electrical checks ensure that the logic and signalling do not violate user-specified limits on key electrical parameters such as virtual ground voltages and currents.
"Leakage current is the big stumbling block to Moore's law, and MTCMOS Power-gating is one of the most effective ways to reduce leakage currents and overall power consumption", explained Prof Takayasu Sakurai of the University of Tokyo.
"Power-gating optimisation, however, has until now not been fully realised in a practical design environment.
Thus, this joint development by Toshiba and Sequence Design will be of great value to both VLSI designers and VLSI customers.
Additionally, the collaboration between the circuit design team and the EDA team is very significant since the solution to recent deep submicron issues requires both circuit knowledge and EDA expertise".
The addition of MTCMOS technology to Sequence's PhysicalStudio leverages the company's experience in low-power design tools as part of its NanoCool initiative, a joint venture between semiconductor designers, EDA tool vendors, IP companies, and library suppliers, to provide a complete flow offering concurrent power management, timing and signal integrity capabilities to achieve rapid design closure at 90 nanometres and below.
PhysicalStudio optimises chip timing and signal-integrity issues concurrently, both before and after routing.
It is fully interoperable with industry-standard routing tools, permitting existing physical design flows to reach fast, predictable design closure.
PhysicalStudio allows system-on-chip designers to: reach 35% higher clock speeds; achieve a 5-15% reduction in power over traditional physical design flows; compensate for signal-integrity effects, such as crosstalk-induced "setup" violations and "hold" violations and functional "glitch" errors; accurately predict and immunise against noise during placement; and surgically correct timing and signal-integrity issues "along the route" using a patent-pending FullContext post-route technique.
By unifying placement-driven optimisation and post-route optimisation into a single engine, the product ensures that every net in a design is correctly driven and all timing and signal integrity violations are eliminated.
PhysicalStudio operates on large, hierarchical designs with varying abstractions at the top-level such as register-bounded blocks, Stamp and Lib.
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