Parasitic extraction tool aids RF chipset design

As the sales leader in the extremely hot 802.11 WLAN market, Intersil Corp had to be sure the tools it chose for RF design would guarantee good results, and ensure time-to-market goals were met.

As the sales leader in the extremely hot 802.11 WLAN market, Intersil Corp had to be sure the tools it chose for RF design would guarantee good results, and ensure time-to-market goals were met.

"Sequence's Columbus-AMS, acting as a critical component of an SoC tool suite, enables the design of RF, analogue and quasi-digital sections with confidence", said Yiqun Lin, Intersil staff engineer, Wireless Networking Product Group.

He added that Columbus fits in seamlessly with the company's Cadence analogue flow, adding multiple benefits, with no negative productivity impact.

Columbus-AMS is part of Sequence's ExtractionStage, a suite of high-performance design tools tuned for complex multi-million-gate SoCs and analogue/mixed-signal design.

Capable of eliminating chip failure due to incorrect interconnect parasitics, Columbus-AMS automatically generates accurate parasitics within 5% of measured silicon, eliminating costly and wasteful guard-banding of high-frequency circuits.

"Sequence's patented RLC extraction technology is proving to be a critical differentiator between RF design success and failure", said Vic Kulkarni, Sequence President and CEO.

"As we push the boundaries of analogue/mixed signal design, it is imperative that we continue to provide the means to extract these parasitics with unequalled speed and accuracy".

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