Product category:
Memory Devices and Modules
News Release from: Spansion | Subject: MirrorBit Eclipse architecture
Edited by the Electronicstalk Editorial
Team on 06 April 2007
Variety of Flash memory types on a
single chip
MirrorBit Eclipse architecture combines MirrorBit NOR, ORNAND and quad Flash memory on a single die, enabling smart mobile phones and multimedia portable devices with high performance and lower costs.
Flash memory specialist Spansion has announced its MirrorBit Eclipse architecture that combines MirrorBit NOR, ORNAND and quad Flash memory on a single die Compatible with existing chipsets, the MirrorBit Eclipse architecture can be adopted quickly to enable feature phones and multimedia portable devices with high performance and lower costs
This article was originally published on Electronicstalk on 7 Apr 2008 at 8.00am (UK)
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"The MirrorBit Eclipse architecture is the result of a multi-year strategy to leverage a single technology, MirrorBit, to develop a broad range of solutions including NOR, ORNAND and Quad solutions to meet customers' requirements", says Bertrand Cambou, President and CEO of Spansion.
"Now with the MirrorBit Eclipse architecture, we will bring together all three solutions on a single die to deliver a powerful combination not previously possible in the industry".
Further reading
Next-generation ORNAND targets NAND applications
MirrorBit ORNAND2 architecture will use a SONOS-like memory cell connected in a NAND memory array at 45nm, featuring fast write performance with high packing density.
NOR Flash is ready for Chinese handset designs
Prequalification of Flash memory will enable manufacturers to get cost-effective, high-performance phones to market faster in China and other high-growth regions.
"MirrorBit Eclipse architecture's ease-of-use and compatibility with existing platforms can enable handset OEMs to rapidly bring to market innovative feature phones at the same or lower costs to hit industry standard price points".
With the increase of digital content on phones and multimedia portable devices such as pictures, music and video, the MirrorBit Eclipse architecture can enable improved performance such as fast application loading and boot times as well as fast image storage and retrieval.
Spansion strives to enable handset OEMs to reduce costs and enable faster programming time to produce phones more quickly.
By taking advantage of the MirrorBit Eclipse architecture with its NOR interface and XIP (execute-in-place) approach, handset OEMs can reduce the amount of DRAM in the system.
As a result of the MirrorBit NOR, ORNAND and quad combination, performance improvements such as running code at blasting speeds and storing large amounts of multimedia content can be achieved on a single die.
Additionally, the MirrorBit Eclipse architecture integrates a programmable microcontroller, which replaces the conventional state machine typically used in Flash memory and also supports built-in self test (BIST).
MirrorBit technology's ability to efficiently integrate logic enables a production process that is more flexible and faster, enabling OEMs to get phones faster to market.
The company expects first silicon in Q3, and plans to sample 65nm MirrorBit Eclipse solutions built from 300mm wafers at its SP1 facility later this year.
Based on 2bit per cell MirrorBit technology, these solutions will have the ability to run code at the high speed of traditional NOR, WHILE moving multimedia at very fast data rates.
At 45nm, the solutions are planned to include both 2bit per cell and 4bit per cell storage, significantly increasing the density, and enabling the seamless combination of high- performance code storage with large blocks of multimedia storage capacity.
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