Product category:
Memory Devices and Modules
News Release from: Spansion
Edited by the Electronicstalk Editorial
Team on 20 March 2008
Manufacturing efficiency boosts Flash
output
Increased output from both its its Austin, Texas and Aizu-Wakamatsu, Japan fabs will enable Spansion to reduce its dependencies on outside foundry support.
Improvements in manufacturing efficiency are allowing Spansion to reduce its reliance on foundry and subcontractors by approximately US $50 million per quarter in the first half of fiscal 2008 compared with the second half of fiscal 2007 Manufacturing efficiencies resulting in increased output in its Austin, Texas Fab25 and Aizu-Wakamatsu, Japan-based SP1 fab is expected to allow Spansion to reduce its dependencies on outside foundry support, particularly for 90nm products
This article was originally published on Electronicstalk on 11 Nov 2004 at 8.00am (UK)
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Mobile memory scales from 16Mbit to 5Gbit
Spansion has announced plans for new Flash memory devices that will simplify mobile phone design with a single Flash memory platform.
Roadmap scaling to 8Gbit Flash memory
MirrorBit technology is the centerpiece of a plan to become overall Flash market leader and outlines plans to scale Spansion's technology to 8Gbit densities on 65nm lithography.
In addition, new testing capabilities are resulting in significant increases in both throughput and yield, specifically on 65nm products including the company's leading-edge MirrorBit technology Flash memory products.
According to Bertrand Cambou, Spansion President and CEO: "Last year, Spansion committed to reducing dependencies on external foundry sources and streamlining our own manufacturing and test capabilities, with the ultimate goal being significant cost savings".
"With the exceptional performance of our worldwide manufacturing and engineering teams, we have met that challenge and are committed to continuing to prove our ability to lead in this highly competitive field".
Further reading
Flash memories adapt to market demands
MirrorBit ORNAND solutions are optimised for data storage in automotive electronics, consumer, networking and wireless segments of the Flash memory market.
Flash chips feature in automotive control module
Analog Devices is combining Spansion known good die (KGD) Flash memory with its Blackfin processor in a multichip module for products supporting the automotive market.
Novel architecture doubles Flash density
Spansion has demonstrated working silicon of the industry's first 4bit-per-cell Flash memory technology, produced at its Fab 25 production facility in Austin, Texas.
In addition to Spansion's internal manufacturing focus, the company plans to continue its long-term partnership strategy with a select group of subcontractors, such as ChipMOS for wafer sort and SMIC for wafer foundry.
The SMIC agreement is expected to result in 65nm, 300mm wafers being produced before the end of fiscal 2008.
In Austin, Texas, Spansion's Fab25 continues to exceed the company's expectations in both yield and output on its 90nm products.
At the same time, SP1 in Japan has ramped up on 300mm wafers, reaching starts of 2000 wafers per week on 65nm MirrorBit technology Flash memory products.
The combination of the two facilities' success will allow Spansion to reduce its reliance on external foundry sources.
SP1 is colocated in Aizu-Wakamatsu, Japan with Spansion's other fab, JV3, and is the first fabrication facility constructed by Spansion since it became an independent company.
Plans for SP1 include an aggressive migration plan to 45nm in fiscal 2009, which is expected to provide additional cost efficiencies.
Spansion has also been developing new capabilities for wafer-level testing and built-in self test (BIST), designed for integration with 65nm lines.
The implementation of these capabilities is expected to result in higher throughput, increased yields and lowered costs.
By integrating these leading-edge testing capabilities into its existing facilities, Spansion has reduced its dependencies on external test vendors, which has resulted in cost reductions.
Wafer-level testing streamlines the overall testing process by conducting electrical testing while the die are still in wafer form, reducing the amount of time spent on identifying design or processing problems.
Specifically designed to reduce costs associated with testing, BIST reduces both the test cycle duration and the complexity of the test set-up, which directly reduces the need for automated test equipment (ATE).
These advanced techniques for testing provide faster, more accurate measurement results, providing an increased return on investment.
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